From 8462ea3d5ba24ca8dfaa5639e00d90f97e369c69 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 12 Jan 2018 12:29:27 -0800 Subject: [PATCH] coreplex => subsystem --- src/main/scala/amba/axi4/AsyncCrossing.scala | 2 +- src/main/scala/devices/debug/Periphery.scala | 2 +- src/main/scala/devices/tilelink/BootROM.scala | 6 ++-- .../scala/devices/tilelink/BusBypass.scala | 2 +- .../tilelink/{Clint.scala => CLINT.scala} | 20 ++++++------- src/main/scala/devices/tilelink/Error.scala | 2 +- src/main/scala/devices/tilelink/MaskROM.scala | 2 +- src/main/scala/devices/tilelink/Plic.scala | 4 +-- src/main/scala/devices/tilelink/Zero.scala | 2 +- src/main/scala/diplomacy/Resources.scala | 2 +- src/main/scala/groundtest/Configs.scala | 4 +-- src/main/scala/groundtest/Coreplex.scala | 8 ++--- src/main/scala/groundtest/TestHarness.scala | 2 +- src/main/scala/groundtest/Tile.scala | 2 +- src/main/scala/rocket/BTB.scala | 2 +- src/main/scala/rocket/DCache.scala | 2 +- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/rocket/ICache.scala | 2 +- src/main/scala/rocket/PTW.scala | 2 +- src/main/scala/rocket/TLB.scala | 2 +- .../BaseSubsystem.scala} | 16 +++++----- .../{coreplex => subsystem}/Configs.scala | 8 ++--- .../CrossingWrapper.scala | 30 +++++++++---------- .../{coreplex => subsystem}/FrontBus.scala | 2 +- .../{coreplex => subsystem}/HasTiles.scala | 2 +- .../InterruptBus.scala | 2 +- .../{coreplex => subsystem}/MemoryBus.scala | 10 +++---- .../PeripheryBus.scala | 2 +- .../scala/{coreplex => subsystem}/Ports.scala | 2 +- .../scala/{coreplex => subsystem}/RTC.scala | 6 ++-- .../{coreplex => subsystem}/ResetVector.scala | 2 +- .../RocketSubsystem.scala} | 20 ++++++------- .../{coreplex => subsystem}/SystemBus.scala | 2 +- src/main/scala/system/Configs.scala | 6 ++-- .../scala/system/ExampleRocketSystem.scala | 8 ++--- src/main/scala/system/Generator.scala | 6 ++-- src/main/scala/tile/BaseTile.scala | 4 +-- src/main/scala/tile/Interrupts.scala | 4 +-- src/main/scala/tile/L1Cache.scala | 2 +- src/main/scala/tile/LazyRoCC.scala | 2 +- src/main/scala/tile/RocketTile.scala | 4 +-- src/main/scala/tilelink/AsyncCrossing.scala | 2 +- src/main/scala/unittest/Configs.scala | 10 +++---- src/main/scala/util/GeneratorUtils.scala | 2 +- 45 files changed, 114 insertions(+), 114 deletions(-) rename src/main/scala/devices/tilelink/{Clint.scala => CLINT.scala} (83%) rename src/main/scala/{coreplex/BaseCoreplex.scala => subsystem/BaseSubsystem.scala} (86%) rename src/main/scala/{coreplex => subsystem}/Configs.scala (98%) rename src/main/scala/{coreplex => subsystem}/CrossingWrapper.scala (90%) rename src/main/scala/{coreplex => subsystem}/FrontBus.scala (97%) rename src/main/scala/{coreplex => subsystem}/HasTiles.scala (97%) rename src/main/scala/{coreplex => subsystem}/InterruptBus.scala (98%) rename src/main/scala/{coreplex => subsystem}/MemoryBus.scala (90%) rename src/main/scala/{coreplex => subsystem}/PeripheryBus.scala (97%) rename src/main/scala/{coreplex => subsystem}/Ports.scala (99%) rename src/main/scala/{coreplex => subsystem}/RTC.scala (84%) rename src/main/scala/{coreplex => subsystem}/ResetVector.scala (86%) rename src/main/scala/{coreplex/RocketCoreplex.scala => subsystem/RocketSubsystem.scala} (91%) rename src/main/scala/{coreplex => subsystem}/SystemBus.scala (98%) diff --git a/src/main/scala/amba/axi4/AsyncCrossing.scala b/src/main/scala/amba/axi4/AsyncCrossing.scala index 3110ef23..ed2dd7f2 100644 --- a/src/main/scala/amba/axi4/AsyncCrossing.scala +++ b/src/main/scala/amba/axi4/AsyncCrossing.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing} +import freechips.rocketchip.subsystem.{CrossingWrapper, AsynchronousCrossing} class AXI4AsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 2496b15d..4d18ec7a 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug import Chisel._ import chisel3.core.{IntParam, Input, Output} import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.HasPeripheryBus +import freechips.rocketchip.subsystem.HasPeripheryBus import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.jtag._ diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala index 1110171c..d4def318 100644 --- a/src/main/scala/devices/tilelink/BootROM.scala +++ b/src/main/scala/devices/tilelink/BootROM.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ @@ -58,7 +58,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec } } -/** Adds a boot ROM that contains the DTB describing the system's coreplex. */ +/** Adds a boot ROM that contains the DTB describing the system's subsystem. */ trait HasPeripheryBootROM extends HasPeripheryBus { val dtb: DTB private val params = p(BootROMParams) @@ -74,7 +74,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus { bootrom.node := pbus.toVariableWidthSlaves } -/** Coreplex will power-on running at 0x10040 (BootROM) */ +/** Subsystem will power-on running at 0x10040 (BootROM) */ trait HasPeripheryBootROMModuleImp extends LazyModuleImp with HasResetVectorWire { val outer: HasPeripheryBootROM diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala index 9c99a3a1..91acd329 100644 --- a/src/main/scala/devices/tilelink/BusBypass.scala +++ b/src/main/scala/devices/tilelink/BusBypass.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.HasPeripheryBus +import freechips.rocketchip.subsystem.HasPeripheryBus import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ diff --git a/src/main/scala/devices/tilelink/Clint.scala b/src/main/scala/devices/tilelink/CLINT.scala similarity index 83% rename from src/main/scala/devices/tilelink/Clint.scala rename to src/main/scala/devices/tilelink/CLINT.scala index 75f16ab7..12d2a8a5 100644 --- a/src/main/scala/devices/tilelink/Clint.scala +++ b/src/main/scala/devices/tilelink/CLINT.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.HasPeripheryBus +import freechips.rocketchip.subsystem.HasPeripheryBus import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ @@ -12,7 +12,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import scala.math.{min,max} -object ClintConsts +object CLINTConsts { def msipOffset(hart: Int) = hart * msipBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes @@ -25,16 +25,16 @@ object ClintConsts def ints = 2 } -case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) +case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0) { - def address = AddressSet(baseAddress, ClintConsts.size-1) + def address = AddressSet(baseAddress, CLINTConsts.size-1) } -case object ClintKey extends Field(ClintParams()) +case object CLINTKey extends Field(CLINTParams()) -class CoreplexLocalInterrupter(params: ClintParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule +class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { - import ClintConsts._ + import CLINTConsts._ // clint0 => at most 4095 devices val device = new SimpleDevice("clint", Seq("riscv,clint0")) { @@ -90,8 +90,8 @@ class CoreplexLocalInterrupter(params: ClintParams, beatBytes: Int)(implicit p: } } -/** Trait that will connect a Clint to a coreplex */ -trait HasPeripheryClint extends HasPeripheryBus { - val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey), pbus.beatBytes)) +/** Trait that will connect a CLINT to a subsystem */ +trait HasPeripheryCLINT extends HasPeripheryBus { + val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes)) clint.node := pbus.toVariableWidthSlaves } diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index ebe66ab2..b8b1de94 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.HasSystemBus +import freechips.rocketchip.subsystem.HasSystemBus import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala index d40526ae..a5e15d45 100644 --- a/src/main/scala/devices/tilelink/MaskROM.scala +++ b/src/main/scala/devices/tilelink/MaskROM.scala @@ -3,7 +3,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ -import freechips.rocketchip.coreplex.{HasPeripheryBus} +import freechips.rocketchip.subsystem.{HasPeripheryBus} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala index c0a0b75b..f2aa9af2 100644 --- a/src/main/scala/devices/tilelink/Plic.scala +++ b/src/main/scala/devices/tilelink/Plic.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus} +import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.tilelink._ @@ -268,7 +268,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends } } -/** Trait that will connect a PLIC to a coreplex */ +/** Trait that will connect a PLIC to a subsystem */ trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus { val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)) plic.node := pbus.toVariableWidthSlaves diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala index 229fc55d..33d46f36 100644 --- a/src/main/scala/devices/tilelink/Zero.scala +++ b/src/main/scala/devices/tilelink/Zero.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink import Chisel._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.HasMemoryBus +import freechips.rocketchip.subsystem.HasMemoryBus import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/diplomacy/Resources.scala b/src/main/scala/diplomacy/Resources.scala index b6729874..58ba6415 100644 --- a/src/main/scala/diplomacy/Resources.scala +++ b/src/main/scala/diplomacy/Resources.scala @@ -211,7 +211,7 @@ case class Resource(owner: Device, key: String) } } -/** The resource binding scope for a LazyModule that generates a device tree (currently Coreplex only). */ +/** The resource binding scope for a LazyModule that generates a device tree (currently Subsystem only). */ trait BindingScope { this: LazyModule => diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 067202a8..c9aca2a8 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -5,13 +5,13 @@ package freechips.rocketchip.groundtest import Chisel._ import freechips.rocketchip.config.Config -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.{DCacheParams} import freechips.rocketchip.tile.{MaxHartIdBits, XLen} /** Actual testing target Configs */ -class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseCoreplexConfig) +class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseSubsystemConfig) class TraceGenBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new TraceGenConfig) diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index ba044c46..b2cf5971 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -7,7 +7,7 @@ import Chisel._ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ @@ -15,7 +15,7 @@ import scala.math.max case object TileId extends Field[Int] -class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex +class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem with HasMasterAXI4MemPort with HasPeripheryTestRAMSlave with HasInterruptBus { @@ -37,10 +37,10 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes)) pbusRAM.node := pbus.toVariableWidthSlaves - override lazy val module = new GroundTestCoreplexModule(this) + override lazy val module = new GroundTestSubsystemModule(this) } -class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexModule(_outer) +class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModule(_outer) with HasMasterAXI4MemPortModuleImp { val success = IO(Bool(OUTPUT)) diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala index 6f2f447e..877ad08d 100644 --- a/src/main/scala/groundtest/TestHarness.scala +++ b/src/main/scala/groundtest/TestHarness.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.LazyModule class TestHarness(implicit p: Parameters) extends Module { val io = new Bundle { val success = Bool(OUTPUT) } - val dut = Module(LazyModule(new GroundTestCoreplex).module) + val dut = Module(LazyModule(new GroundTestSubsystem).module) io.success := dut.success dut.connectSimAXIMem() } diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index e38ebb05..2eb6593b 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.groundtest import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.rocket.{DCache, RocketCoreParams} import freechips.rocketchip.tile._ diff --git a/src/main/scala/rocket/BTB.scala b/src/main/scala/rocket/BTB.scala index 90413d0b..0693b1a6 100644 --- a/src/main/scala/rocket/BTB.scala +++ b/src/main/scala/rocket/BTB.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.rocket import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.HasCoreParameters import freechips.rocketchip.util._ diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 83d1df9c..2c5f2408 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.rocket import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex.{RocketTilesKey} +import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.diplomacy.{AddressSet, RegionType} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index bf053231..4eae78ca 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -7,7 +7,7 @@ import Chisel._ import Chisel.ImplicitConversions._ import chisel3.core.withReset import freechips.rocketchip.config._ -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 030c2ce5..17b53b73 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.rocket import Chisel._ import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index abb68428..ac2219e1 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.rocket import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex.RocketTilesKey +import freechips.rocketchip.subsystem.RocketTilesKey import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 9d63a90b..1e7b8117 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.rocket import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 9ecae1e0..5eca04ec 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -7,7 +7,7 @@ import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/subsystem/BaseSubsystem.scala similarity index 86% rename from src/main/scala/coreplex/BaseCoreplex.scala rename to src/main/scala/subsystem/BaseSubsystem.scala index 94c90a5c..89114c45 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.Parameters @@ -9,14 +9,14 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ -/** BareCoreplex is the root class for creating a coreplex sub-system */ -abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope { +/** BareSubsystem is the root class for creating a subsystem */ +abstract class BareSubsystem(implicit p: Parameters) extends LazyModule with BindingScope { lazy val dts = DTS(bindingTree) lazy val dtb = DTB(dts) lazy val json = JSON(bindingTree) } -abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyModuleImp(_outer) { +abstract class BareSubsystemModule[+L <: BareSubsystem](_outer: L) extends LazyModuleImp(_outer) { val outer = _outer ElaborationArtefacts.add("graphml", outer.graphML) ElaborationArtefacts.add("dts", outer.dts) @@ -25,13 +25,13 @@ abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMod println(outer.dts) } -/** Base Coreplex class with no peripheral devices or ports added */ -abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex +/** Base Subsystem class with no peripheral devices or ports added */ +abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem with HasInterruptBus with HasSystemBus with HasPeripheryBus with HasMemoryBus { - override val module: BaseCoreplexModule[BaseCoreplex] + override val module: BaseSubsystemModule[BaseSubsystem] // Make topManagers an Option[] so as to avoid LM name reflection evaluating it... lazy val topManagers = Some(ManagerUnification(sharedMemoryTLEdge.manager.managers)) @@ -59,7 +59,7 @@ abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex } } -abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) { +abstract class BaseSubsystemModule[+L <: BaseSubsystem](_outer: L) extends BareSubsystemModule(_outer) { println("Generated Address Map") private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1 private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s" diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/subsystem/Configs.scala similarity index 98% rename from src/main/scala/coreplex/Configs.scala rename to src/main/scala/subsystem/Configs.scala index b5840a41..189e054a 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -1,7 +1,7 @@ // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config._ @@ -13,7 +13,7 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -class BaseCoreplexConfig extends Config ((site, here, up) => { +class BaseSubsystemConfig extends Config ((site, here, up) => { // Tile parameters case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ case XLen => 64 // Applies to all cores @@ -155,8 +155,8 @@ class WithIncoherentTiles extends Config((site, here, up) => { case RocketCrossingKey => up(RocketCrossingKey, site) map { r => r.copy(master = r.master.copy(cork = Some(true))) } - case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex => - val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)(coreplex.p)) + case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { subsystem => + val ww = LazyModule(new TLWidthWidget(subsystem.sbusBeatBytes)(subsystem.p)) (ww.node, ww.node, () => None) }) }) diff --git a/src/main/scala/coreplex/CrossingWrapper.scala b/src/main/scala/subsystem/CrossingWrapper.scala similarity index 90% rename from src/main/scala/coreplex/CrossingWrapper.scala rename to src/main/scala/subsystem/CrossingWrapper.scala index f76b058c..d479890e 100644 --- a/src/main/scala/coreplex/CrossingWrapper.scala +++ b/src/main/scala/subsystem/CrossingWrapper.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config._ @@ -11,16 +11,16 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ /** Enumerates the three types of clock crossing between tiles and system bus */ -sealed trait CoreplexClockCrossing +sealed trait SubsystemClockCrossing { def sameClock = this match { case _: SynchronousCrossing => true case _ => false } } -case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing -case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing -case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing +case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends SubsystemClockCrossing +case class RationalCrossing(direction: RationalDirection = FastToSlow) extends SubsystemClockCrossing +case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends SubsystemClockCrossing private case class CrossingCheck(out: Boolean, source: BaseNode, sink: BaseNode) @@ -77,13 +77,13 @@ trait HasCrossingMethods extends LazyModule with LazyScope def crossTLRationalIn (direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(false)(direction) def crossTLRationalOut(direction: RationalDirection)(implicit p: Parameters): TLNode = crossTLRationalInOut(true )(direction) - def crossTLIn(arg: CoreplexClockCrossing)(implicit p: Parameters): TLNode = arg match { + def crossTLIn(arg: SubsystemClockCrossing)(implicit p: Parameters): TLNode = arg match { case x: SynchronousCrossing => crossTLSyncIn(x.params) case x: AsynchronousCrossing => crossTLAsyncIn(x.depth, x.sync) case x: RationalCrossing => crossTLRationalIn(x.direction) } - def crossTLOut(arg: CoreplexClockCrossing)(implicit p: Parameters): TLNode = arg match { + def crossTLOut(arg: SubsystemClockCrossing)(implicit p: Parameters): TLNode = arg match { case x: SynchronousCrossing => crossTLSyncOut(x.params) case x: AsynchronousCrossing => crossTLAsyncOut(x.depth, x.sync) case x: RationalCrossing => crossTLRationalOut(x.direction) @@ -112,13 +112,13 @@ trait HasCrossingMethods extends LazyModule with LazyScope def crossAXI4AsyncIn (depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = crossAXI4AsyncInOut(false)(depth, sync) def crossAXI4AsyncOut(depth: Int = 8, sync: Int = 3)(implicit p: Parameters): AXI4Node = crossAXI4AsyncInOut(true )(depth, sync) - def crossAXI4In(arg: CoreplexClockCrossing)(implicit p: Parameters): AXI4Node = arg match { + def crossAXI4In(arg: SubsystemClockCrossing)(implicit p: Parameters): AXI4Node = arg match { case x: SynchronousCrossing => crossAXI4SyncIn(x.params) case x: AsynchronousCrossing => crossAXI4AsyncIn(x.depth, x.sync) case x: RationalCrossing => throw new IllegalArgumentException("AXI4 Rational crossing unimplemented") } - def crossAXI4Out(arg: CoreplexClockCrossing)(implicit p: Parameters): AXI4Node = arg match { + def crossAXI4Out(arg: SubsystemClockCrossing)(implicit p: Parameters): AXI4Node = arg match { case x: SynchronousCrossing => crossAXI4SyncOut(x.params) case x: AsynchronousCrossing => crossAXI4AsyncOut(x.depth, x.sync) case x: RationalCrossing => throw new IllegalArgumentException("AXI4 Rational crossing unimplemented") @@ -163,26 +163,26 @@ trait HasCrossingMethods extends LazyModule with LazyScope def crossIntRationalIn (alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(false)(alreadyRegistered) def crossIntRationalOut(alreadyRegistered: Boolean = false)(implicit p: Parameters): IntNode = crossIntRationalInOut(true )(alreadyRegistered) - def crossIntIn(arg: CoreplexClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match { + def crossIntIn(arg: SubsystemClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match { case x: SynchronousCrossing => crossIntSyncIn(alreadyRegistered) case x: AsynchronousCrossing => crossIntAsyncIn(x.sync, alreadyRegistered) case x: RationalCrossing => crossIntRationalIn(alreadyRegistered) } - def crossIntOut(arg: CoreplexClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match { + def crossIntOut(arg: SubsystemClockCrossing, alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = arg match { case x: SynchronousCrossing => crossIntSyncOut(alreadyRegistered) case x: AsynchronousCrossing => crossIntAsyncOut(x.sync, alreadyRegistered) case x: RationalCrossing => crossIntRationalOut(alreadyRegistered) } - def crossIntIn (arg: CoreplexClockCrossing)(implicit p: Parameters): IntNode = crossIntIn (arg, false) - def crossIntOut(arg: CoreplexClockCrossing)(implicit p: Parameters): IntNode = crossIntOut(arg, false) + def crossIntIn (arg: SubsystemClockCrossing)(implicit p: Parameters): IntNode = crossIntIn (arg, false) + def crossIntOut(arg: SubsystemClockCrossing)(implicit p: Parameters): IntNode = crossIntOut(arg, false) } trait HasCrossing extends HasCrossingMethods { this: LazyModule => - val crossing: CoreplexClockCrossing + val crossing: SubsystemClockCrossing def crossTLIn (implicit p: Parameters): TLNode = crossTLIn (crossing) def crossTLOut (implicit p: Parameters): TLNode = crossTLOut (crossing) @@ -195,4 +195,4 @@ trait HasCrossing extends HasCrossingMethods def crossIntOut(alreadyRegistered: Boolean)(implicit p: Parameters): IntNode = crossIntOut(crossing, alreadyRegistered) } -class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossing +class CrossingWrapper(val crossing: SubsystemClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossing diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala similarity index 97% rename from src/main/scala/coreplex/FrontBus.scala rename to src/main/scala/subsystem/FrontBus.scala index adab063a..a55852f6 100644 --- a/src/main/scala/coreplex/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.{Field, Parameters} diff --git a/src/main/scala/coreplex/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala similarity index 97% rename from src/main/scala/coreplex/HasTiles.scala rename to src/main/scala/subsystem/HasTiles.scala index 49a958f8..48050869 100644 --- a/src/main/scala/coreplex/HasTiles.scala +++ b/src/main/scala/subsystem/HasTiles.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import chisel3.experimental.dontTouch diff --git a/src/main/scala/coreplex/InterruptBus.scala b/src/main/scala/subsystem/InterruptBus.scala similarity index 98% rename from src/main/scala/coreplex/InterruptBus.scala rename to src/main/scala/subsystem/InterruptBus.scala index a9def505..8a19d10f 100644 --- a/src/main/scala/coreplex/InterruptBus.scala +++ b/src/main/scala/subsystem/InterruptBus.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.{Field, Parameters} diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala similarity index 90% rename from src/main/scala/coreplex/MemoryBus.scala rename to src/main/scala/subsystem/MemoryBus.scala index 105f132b..a401ecc5 100644 --- a/src/main/scala/coreplex/MemoryBus.scala +++ b/src/main/scala/subsystem/MemoryBus.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config._ @@ -22,11 +22,11 @@ case object BroadcastKey extends Field(BroadcastParams()) case class BankedL2Params( nMemoryChannels: Int = 1, nBanksPerChannel: Int = 1, - coherenceManager: HasMemoryBus => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { coreplex => - implicit val p = coreplex.p + coherenceManager: HasMemoryBus => (TLInwardNode, TLOutwardNode, () => Option[Bool]) = { subsystem => + implicit val p = subsystem.p val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey) - val bh = LazyModule(new TLBroadcast(coreplex.memBusBlockBytes, nTrackers, bufferless)) - val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)) + val bh = LazyModule(new TLBroadcast(subsystem.memBusBlockBytes, nTrackers, bufferless)) + val ww = LazyModule(new TLWidthWidget(subsystem.sbusBeatBytes)) ww.node :*= bh.node (bh.node, ww.node, () => None) }) { diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala similarity index 97% rename from src/main/scala/coreplex/PeripheryBus.scala rename to src/main/scala/subsystem/PeripheryBus.scala index 7b56f1ec..6c52bd92 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/subsystem/PeripheryBus.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.{Field, Parameters} diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/subsystem/Ports.scala similarity index 99% rename from src/main/scala/coreplex/Ports.scala rename to src/main/scala/subsystem/Ports.scala index 438e0d1e..864b86b8 100644 --- a/src/main/scala/coreplex/Ports.scala +++ b/src/main/scala/subsystem/Ports.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.{Field, Parameters} diff --git a/src/main/scala/coreplex/RTC.scala b/src/main/scala/subsystem/RTC.scala similarity index 84% rename from src/main/scala/coreplex/RTC.scala rename to src/main/scala/subsystem/RTC.scala index e21e29e1..be413e84 100644 --- a/src/main/scala/coreplex/RTC.scala +++ b/src/main/scala/subsystem/RTC.scala @@ -1,13 +1,13 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.diplomacy.{LazyModuleImp, DTSTimebase} -import freechips.rocketchip.devices.tilelink.HasPeripheryClint +import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT trait HasRTCModuleImp extends LazyModuleImp { - val outer: HasPeripheryClint + val outer: HasPeripheryCLINT private val pbusFreq = outer.p(PeripheryBusKey).frequency private val rtcFreq = outer.p(DTSTimebase) private val internalPeriod: BigInt = pbusFreq / rtcFreq diff --git a/src/main/scala/coreplex/ResetVector.scala b/src/main/scala/subsystem/ResetVector.scala similarity index 86% rename from src/main/scala/coreplex/ResetVector.scala rename to src/main/scala/subsystem/ResetVector.scala index d66de529..56366d17 100644 --- a/src/main/scala/coreplex/ResetVector.scala +++ b/src/main/scala/subsystem/ResetVector.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/subsystem/RocketSubsystem.scala similarity index 91% rename from src/main/scala/coreplex/RocketCoreplex.scala rename to src/main/scala/subsystem/RocketSubsystem.scala index db3702bd..5c512dad 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/subsystem/RocketSubsystem.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import chisel3.internal.sourceinfo.SourceInfo @@ -18,7 +18,7 @@ case class TileMasterPortParams( addBuffers: Int = 0, cork: Option[Boolean] = None) { - def adapt(coreplex: HasPeripheryBus) + def adapt(subsystem: HasPeripheryBus) (masterNode: TLOutwardNode) (implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u)))) @@ -33,22 +33,22 @@ case class TileSlavePortParams( addBuffers: Int = 0, blockerCtrlAddr: Option[BigInt] = None) { - def adapt(coreplex: HasPeripheryBus) + def adapt(subsystem: HasPeripheryBus) (slaveNode: TLInwardNode) (implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = { val tile_slave_blocker = blockerCtrlAddr - .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes)) + .map(BasicBusBlockerParams(_, subsystem.pbus.beatBytes, subsystem.sbus.beatBytes)) .map(bp => LazyModule(new BasicBusBlocker(bp))) - tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } + tile_slave_blocker.foreach { _.controlNode := subsystem.pbus.toVariableWidthSlaves } (Seq() ++ tile_slave_blocker.map(_.node) ++ TLBuffer.chain(addBuffers)) .foldLeft(slaveNode)(_ :*= _) } } case class RocketCrossingParams( - crossingType: CoreplexClockCrossing = SynchronousCrossing(), + crossingType: SubsystemClockCrossing = SynchronousCrossing(), master: TileMasterPortParams = TileMasterPortParams(), slave: TileSlavePortParams = TileSlavePortParams()) { def knownRatio: Option[Int] = crossingType match { @@ -63,7 +63,7 @@ case object RocketCrossingKey extends Field[Seq[RocketCrossingParams]](List(Rock trait HasRocketTiles extends HasTiles with HasPeripheryBus with HasPeripheryPLIC - with HasPeripheryClint + with HasPeripheryCLINT with HasPeripheryDebug { val module: HasRocketTilesModuleImp @@ -163,13 +163,13 @@ trait HasRocketTilesModuleImp extends HasTilesModuleImp val outer: HasRocketTiles } -class RocketCoreplex(implicit p: Parameters) extends BaseCoreplex +class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem with HasRocketTiles { val tiles = rocketTiles - override lazy val module = new RocketCoreplexModule(this) + override lazy val module = new RocketSubsystemModule(this) } -class RocketCoreplexModule[+L <: RocketCoreplex](_outer: L) extends BaseCoreplexModule(_outer) +class RocketSubsystemModule[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModule(_outer) with HasRocketTilesModuleImp { tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => wire.clock := clock diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala similarity index 98% rename from src/main/scala/coreplex/SystemBus.scala rename to src/main/scala/subsystem/SystemBus.scala index 1f403d95..3d510874 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/subsystem/SystemBus.scala @@ -1,6 +1,6 @@ // See LICENSE.SiFive for license details. -package freechips.rocketchip.coreplex +package freechips.rocketchip.subsystem import Chisel._ import freechips.rocketchip.config.{Field, Parameters} diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala index 5aab4f1f..b7fd2d90 100644 --- a/src/main/scala/system/Configs.scala +++ b/src/main/scala/system/Configs.scala @@ -5,13 +5,13 @@ package freechips.rocketchip.system import Chisel._ import freechips.rocketchip.config.Config -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey} import freechips.rocketchip.diplomacy._ -class WithJtagDTMSystem extends freechips.rocketchip.coreplex.WithJtagDTM +class WithJtagDTMSystem extends freechips.rocketchip.subsystem.WithJtagDTM -class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => { +class BaseConfig extends Config(new BaseSubsystemConfig().alter((site,here,up) => { // DTS descriptive parameters case DTSModel => "freechips,rocketchip-unknown" case DTSCompat => Nil diff --git a/src/main/scala/system/ExampleRocketSystem.scala b/src/main/scala/system/ExampleRocketSystem.scala index 981f7a0d..7460a297 100644 --- a/src/main/scala/system/ExampleRocketSystem.scala +++ b/src/main/scala/system/ExampleRocketSystem.scala @@ -4,12 +4,12 @@ package freechips.rocketchip.system import Chisel._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch -/** Example Top with periphery devices and ports, and a Rocket coreplex */ -class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex +/** Example Top with periphery devices and ports, and a Rocket subsystem */ +class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem with HasAsyncExtInterrupts with HasMasterAXI4MemPort with HasMasterAXI4MMIOPort @@ -19,7 +19,7 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex override lazy val module = new ExampleRocketSystemModule(this) } -class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketCoreplexModule(_outer) +class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModule(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp with HasMasterAXI4MemPortModuleImp diff --git a/src/main/scala/system/Generator.scala b/src/main/scala/system/Generator.scala index db5f69b6..62c1d5ea 100644 --- a/src/main/scala/system/Generator.scala +++ b/src/main/scala/system/Generator.scala @@ -2,13 +2,13 @@ package freechips.rocketchip.system -import freechips.rocketchip.coreplex.RocketTilesKey +import freechips.rocketchip.subsystem.RocketTilesKey import freechips.rocketchip.tile.XLen import freechips.rocketchip.util.GeneratorApp import scala.collection.mutable.LinkedHashSet -/** A Generator for platforms containing Rocket Coreplexes */ +/** A Generator for platforms containing Rocket Subsystemes */ object Generator extends GeneratorApp { val rv64RegrTestNames = LinkedHashSet( @@ -50,7 +50,7 @@ object Generator extends GeneratorApp { override def addTestSuites { import DefaultTestSuites._ val xlen = params(XLen) - // TODO: for now only generate tests for the first core in the first coreplex + // TODO: for now only generate tests for the first core in the first subsystem val tileParams = params(RocketTilesKey).head val coreParams = tileParams.core val vm = coreParams.useVM diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 40f2b8da..4586379d 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config._ -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.rocket._ @@ -122,7 +122,7 @@ trait HasTileParameters { } /** Base class for all Tiles that use TileLink */ -abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing) +abstract class BaseTile(tileParams: TileParams, val crossing: SubsystemClockCrossing) (implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing { def module: BaseTileModuleImp[BaseTile] diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala index 6e81f109..3f012ba5 100644 --- a/src/main/scala/tile/Interrupts.scala +++ b/src/main/scala/tile/Interrupts.scala @@ -18,7 +18,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { val lip = Vec(coreParams.nLocalInterrupts, Bool()) } -// Use diplomatic interrupts to external interrupts from the coreplex into the tile +// Use diplomatic interrupts to external interrupts from the subsystem into the tile trait HasExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode @@ -50,7 +50,7 @@ trait HasExternalInterrupts { this: BaseTile => // TODO: the order of the following two functions must match, and // also match the order which things are connected to the - // per-tile crossbar in coreplex.HasRocketTiles + // per-tile crossbar in subsystem.HasRocketTiles // debug, msip, mtip, meip, seip, lip offsets in CSRs def csrIntMap: List[Int] = { diff --git a/src/main/scala/tile/L1Cache.scala b/src/main/scala/tile/L1Cache.scala index 811a9773..4b0e11d8 100644 --- a/src/main/scala/tile/L1Cache.scala +++ b/src/main/scala/tile/L1Cache.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config.{Parameters, Field} -import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tilelink.ClientMetadata import freechips.rocketchip.util._ diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala index 49dff340..33d70c0c 100644 --- a/src/main/scala/tile/LazyRoCC.scala +++ b/src/main/scala/tile/LazyRoCC.scala @@ -6,7 +6,7 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config._ -import freechips.rocketchip.coreplex._ +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 79b565bf..e4ace503 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tile import Chisel._ import freechips.rocketchip.config._ -import freechips.rocketchip.coreplex.CoreplexClockCrossing +import freechips.rocketchip.subsystem.SubsystemClockCrossing import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ @@ -33,7 +33,7 @@ case class RocketTileParams( class RocketTile( val rocketParams: RocketTileParams, - crossing: CoreplexClockCrossing) + crossing: SubsystemClockCrossing) (implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p) with HasExternalInterrupts with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala index 4e4a9300..8c7d5300 100644 --- a/src/main/scala/tilelink/AsyncCrossing.scala +++ b/src/main/scala/tilelink/AsyncCrossing.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property._ -import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing} +import freechips.rocketchip.subsystem.{CrossingWrapper, AsynchronousCrossing} class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule { diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index 4eb75458..996141b8 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.amba.ahb._ import freechips.rocketchip.amba.apb._ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.config._ -import freechips.rocketchip.coreplex.{BaseCoreplexConfig} +import freechips.rocketchip.subsystem.{BaseSubsystemConfig} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.tilelink._ @@ -79,7 +79,7 @@ class WithTLXbarUnitTests extends Config((site, here, up) => { Module(new TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) } }) -class AMBAUnitTestConfig extends Config(new WithAMBAUnitTests ++ new WithTestDuration(10) ++ new BaseCoreplexConfig) -class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BaseCoreplexConfig) -class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BaseCoreplexConfig) -class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BaseCoreplexConfig) +class AMBAUnitTestConfig extends Config(new WithAMBAUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) +class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) +class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) +class TLXbarUnitTestConfig extends Config(new WithTLXbarUnitTests ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala index 18b1a9b7..4a151cd3 100644 --- a/src/main/scala/util/GeneratorUtils.scala +++ b/src/main/scala/util/GeneratorUtils.scala @@ -108,7 +108,7 @@ trait GeneratorApp extends App with HasGeneratorUtilities { /** Output software test Makefrags, which provide targets for integration testing. */ def generateTestSuiteMakefrags { addTestSuites - writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites + writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites } def addTestSuites {