127 lines
4.2 KiB
Scala
127 lines
4.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem.HasSystemBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int, acquire: Boolean = false)
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{
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require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
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}
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case object ErrorParams extends Field[ErrorParams]
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abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
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(device: SimpleDevice)
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(implicit p: Parameters) extends LazyModule {
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val xfer = TransferSizes(1, params.maxTransfer)
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val atom = TransferSizes(1, params.maxAtomic)
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = params.address,
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resources = device.reg("mem"),
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regionType = if (params.acquire) RegionType.TRACKED else RegionType.UNCACHEABLE,
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executable = true,
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supportsAcquireT = if (params.acquire) xfer else TransferSizes.none,
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supportsAcquireB = if (params.acquire) xfer else TransferSizes.none,
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supportsGet = xfer,
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supportsPutPartial = xfer,
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supportsPutFull = xfer,
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supportsArithmetic = atom,
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supportsLogical = atom,
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supportsHint = xfer,
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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endSinkId = 1, // can receive GrantAck
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minLatency = 1))) // no bypass needed for this device
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}
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/** Adds a /dev/null slave that generates TL error response messages */
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class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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extends DevNullDevice(params, beatBytes)(new SimpleDevice("error-device", Seq("sifive,error0")))
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{
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lazy val module = new LazyModuleImp(this) {
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import TLMessages._
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import TLPermissions._
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val (in, edge) = node.in(0)
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val a = Queue(in.a, 1)
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val da = Wire(in.d)
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val a_last = edge.last(a)
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val da_last = edge.last(da)
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a.ready := (da.ready && da_last) || !a_last
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da.valid := a.valid && a_last
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val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
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da.bits.opcode := a_opcodes(a.bits.opcode)
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da.bits.param := UInt(0) // toT, but error grants must be handled transiently (ie: you don't keep permissions)
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da.bits.size := a.bits.size
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da.bits.source := a.bits.source
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da.bits.sink := UInt(0)
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da.bits.data := UInt(0)
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da.bits.error := Bool(true)
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if (params.acquire) {
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val c = Queue(in.c, 1)
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val dc = Wire(in.d)
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val c_last = edge.last(c)
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val dc_last = edge.last(dc)
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c.ready := (dc.ready && dc_last) || !c_last
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dc.valid := c.valid && c_last
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dc.bits.opcode := ReleaseAck
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dc.bits.param := Vec(toB, toN, toN)(c.bits.param)
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dc.bits.size := c.bits.size
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dc.bits.source := c.bits.source
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dc.bits.sink := UInt(0)
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dc.bits.data := UInt(0)
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dc.bits.error := Bool(true)
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// Combine response channels
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TLArbiter.lowest(edge, in.d, dc, da)
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} else {
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in.d <> da
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}
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// We never probe or issue B requests
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in.b.valid := Bool(false)
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// Sink GrantAcks
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in.e.ready := Bool(true)
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}
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}
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/** Adds a /dev/null slave that does not raise ready for any incoming traffic.
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* !!! WARNING: This device WILL cause your bus to deadlock for as long as you
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* continue to send traffic to it !!!
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*/
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class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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extends DevNullDevice(params, beatBytes)(new SimpleDevice("deadlock-device", Seq("sifive,deadlock0")))
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{
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lazy val module = new LazyModuleImp(this) {
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val (in, _) = node.in(0)
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in.a.ready := Bool(false)
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in.b.valid := Bool(false)
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in.c.ready := Bool(false)
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in.d.valid := Bool(false)
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in.e.ready := Bool(false)
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}
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}
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trait HasSystemErrorSlave extends HasSystemBus {
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private val params = p(ErrorParams)
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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error.node := sbus.toSlave
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}
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