70 lines
2.3 KiB
Scala
70 lines
2.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.subsystem.{HasPeripheryBus}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width: Int = 32)
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case object PeripheryMaskROMKey extends Field[Seq[MaskROMParams]]
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trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
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val maskROMParams = p(PeripheryMaskROMKey)
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val maskROMs = maskROMParams map { params =>
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val maskROM = LazyModule(new TLMaskROM(params))
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maskROM.node := pbus.toFixedWidthSingleBeatSlave(maskROM.beatBytes)
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maskROM
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}
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}
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class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
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val beatBytes = c.width/8
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = AddressSet.misaligned(c.address, c.depth*beatBytes),
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resources = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes)))
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lazy val module = new LazyModuleImp(this) {
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val (in, edge)= node.in(0)
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val rom = ROMGenerator(ROMConfig(c.name, c.depth, c.width))
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rom.io.clock := clock
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rom.io.address := edge.addr_hi(in.a.bits.address - UInt(c.address))(log2Ceil(c.depth)-1, 0)
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rom.io.oe := Bool(true) // active high tri state enable
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rom.io.me := in.a.fire()
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val d_full = RegInit(Bool(false))
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_data = rom.io.q holdUnless RegNext(in.a.fire())
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// Flow control
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when (in.d.fire()) { d_full := Bool(false) }
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when (in.a.fire()) { d_full := Bool(true) }
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in.d.valid := d_full
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in.a.ready := in.d.ready || !d_full
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when (in.a.fire()) {
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d_size := in.a.bits.size
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d_source := in.a.bits.source
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}
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in.d.bits := edge.AccessAck(d_source, d_size, d_data)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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