1
0
rocket-chip/rocket/src/main/scala/util.scala

205 lines
5.9 KiB
Scala
Raw Normal View History

package rocket
2011-11-09 23:52:17 +01:00
import Chisel._
import uncore._
2013-06-13 19:31:04 +02:00
import scala.math._
2014-03-24 12:36:53 +01:00
class BooleanToInt(x: Int) {
def toBoolean: Boolean = if (x != 0) true else false
}
object Util {
2013-08-12 19:39:11 +02:00
implicit def intToUInt(x: Int): UInt = UInt(x)
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def intSeqToUIntSeq(x: Iterable[Int]): Iterable[UInt] = x.map(UInt(_))
implicit def seqToVec[T <: Data](x: Iterable[T]): Vec[T] = Vec(x)
2013-08-12 19:39:11 +02:00
implicit def wcToUInt(c: WideCounter): UInt = c.value
2014-03-24 12:36:53 +01:00
implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
implicit def intToBooleanToInt(x: Int): BooleanToInt = new BooleanToInt(x)
}
import Util._
abstract trait BundleWithConf extends Bundle {
val conf: AnyRef
override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
}
2013-06-13 19:31:04 +02:00
object Str
{
2013-12-10 04:52:47 +01:00
def apply(s: String): UInt = {
2013-06-13 19:31:04 +02:00
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
2013-12-10 04:52:47 +01:00
UInt(i, s.length*8)
2013-06-13 19:31:04 +02:00
}
2013-12-10 04:52:47 +01:00
def apply(x: Char): UInt = {
2013-06-13 19:31:04 +02:00
require(validChar(x))
2013-12-10 04:52:47 +01:00
UInt(x.toInt, 8)
2013-06-13 19:31:04 +02:00
}
2013-12-10 04:52:47 +01:00
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
2013-08-12 19:39:11 +02:00
val rad = UInt(radix)
2013-06-13 19:31:04 +02:00
val w = x.getWidth
require(w > 0)
var q = x
2013-08-24 06:16:28 +02:00
var s = digit(q % rad)
2013-06-13 19:31:04 +02:00
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
2013-08-24 06:16:28 +02:00
s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digit(q % rad)), s)
2013-06-13 19:31:04 +02:00
}
s
}
2013-12-10 04:52:47 +01:00
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
2013-08-12 19:39:11 +02:00
val neg = x < SInt(0)
2013-06-15 09:45:53 +02:00
val abs = x.abs
2013-06-13 19:31:04 +02:00
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
2013-08-12 19:39:11 +02:00
val rad = UInt(radix)
2013-06-13 19:31:04 +02:00
val w = abs.getWidth
require(w > 0)
var q = abs
2013-08-24 06:16:28 +02:00
var s = digit(q % rad)
2013-06-13 19:31:04 +02:00
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
2013-08-12 19:39:11 +02:00
val placeSpace = q === UInt(0)
2013-06-13 19:31:04 +02:00
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
2013-08-24 06:16:28 +02:00
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
2013-06-13 19:31:04 +02:00
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
2013-12-10 04:52:47 +01:00
private def digit(d: UInt): UInt = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
2013-06-13 19:31:04 +02:00
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
// is there a better way to do do this?
def apply(x: Bits, n0: Int) = {
val w = checkWidth(x, n0)
(x(w-1,n0), x(n0-1,0))
}
def apply(x: Bits, n1: Int, n0: Int) = {
val w = checkWidth(x, n1, n0)
(x(w-1,n1), x(n1-1,n0), x(n0-1,0))
}
def apply(x: Bits, n2: Int, n1: Int, n0: Int) = {
val w = checkWidth(x, n2, n1, n0)
(x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0))
}
private def checkWidth(x: Bits, n: Int*) = {
val w = x.getWidth
def decreasing(x: Seq[Int]): Boolean =
if (x.tail.isEmpty) true
else x.head > x.tail.head && decreasing(x.tail)
require(decreasing(w :: n.toList))
w
}
}
// a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = UInt(1))
{
require(inc.getWidth > 0)
private val isWide = width > 2*inc.getWidth
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
2013-08-16 00:28:15 +02:00
private val small = Reg(init=UInt(0, smallWidth))
private val doInc = inc.orR
private val nextSmall =
if (inc.getWidth == 1) small + UInt(1, smallWidth+1)
else Cat(UInt(0,1), small) + inc
when (doInc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) {
2013-08-16 00:28:15 +02:00
val r = Reg(init=UInt(0, width - smallWidth))
when (doInc && nextSmall(smallWidth)) { r := r + UInt(1) }
r
} else null
val value = Cat(large, small)
2013-08-12 19:39:11 +02:00
def := (x: UInt) = {
val w = x.getWidth
small := x(w.min(smallWidth)-1,0)
2013-08-12 19:39:11 +02:00
if (isWide) large := (if (w < smallWidth) UInt(0) else x(w.min(width)-1,smallWidth))
}
2011-12-09 09:42:43 +01:00
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random(log2Up(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).toBits
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR16()
private def round(x: Double): Int =
if (x.toInt.toDouble == x) x.toInt else (x.toInt + 1) & -2
private def partition(value: UInt, slices: Int) =
Vec.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
}
class FlowThroughSerializer[T <: HasTileLinkData](gen: LogicalNetworkIO[T], n: Int, doSer: T => Bool) extends Module {
val io = new Bundle {
val in = Decoupled(gen.clone).flip
val out = Decoupled(gen.clone)
val cnt = UInt(OUTPUT, log2Up(n))
val done = Bool(OUTPUT)
}
require(io.in.bits.payload.data.needWidth() % n == 0)
val narrowWidth = io.in.bits.payload.data.needWidth() / n
val cnt = Reg(init=UInt(0, width = log2Up(n)))
val wrap = cnt === UInt(n-1)
val rbits = Reg(init=io.in.bits)
val active = Reg(init=Bool(false))
val shifter = Vec.fill(n){Bits(width = narrowWidth)}
(0 until n).foreach {
i => shifter(i) := rbits.payload.data((i+1)*narrowWidth-1,i*narrowWidth)
}
io.done := Bool(false)
io.cnt := cnt
io.in.ready := !active
io.out.valid := active || io.in.valid
io.out.bits := io.in.bits
when(!active && io.in.valid) {
when(doSer(io.in.bits.payload)) {
cnt := Mux(io.out.ready, UInt(1), UInt(0))
rbits := io.in.bits
active := Bool(true)
}
io.done := !doSer(io.in.bits.payload)
}
when(active) {
io.out.bits := rbits
io.out.bits.payload.data := shifter(cnt)
when(io.out.ready) {
cnt := cnt + UInt(1)
when(wrap) {
2014-04-15 02:12:30 +02:00
cnt := UInt(0)
io.done := Bool(true)
active := Bool(false)
}
}
}
}