2012-10-16 23:26:33 +02:00
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package uncore
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import Chisel._
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2013-08-02 23:55:06 +02:00
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case class TileLinkConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration, masterXactIdBits: Int, clientXactIdBits: Int, dataBits: Int)
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2013-03-20 22:10:16 +01:00
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2013-08-02 23:55:06 +02:00
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abstract trait TileLinkSubBundle extends Bundle {
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implicit val conf: TileLinkConfiguration
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2013-08-13 08:15:54 +02:00
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override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
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2012-10-16 23:26:33 +02:00
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}
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2013-08-02 23:55:06 +02:00
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trait HasPhysicalAddress extends TileLinkSubBundle {
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2013-08-12 19:36:44 +02:00
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val addr = UInt(width = PADDR_BITS - OFFSET_BITS)
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2012-10-16 23:26:33 +02:00
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}
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2013-08-02 23:55:06 +02:00
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trait HasClientTransactionId extends TileLinkSubBundle {
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val client_xact_id = Bits(width = conf.clientXactIdBits)
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2012-10-16 23:26:33 +02:00
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}
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2013-08-02 23:55:06 +02:00
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trait HasMasterTransactionId extends TileLinkSubBundle {
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val master_xact_id = Bits(width = conf.masterXactIdBits)
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2012-10-16 23:26:33 +02:00
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}
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2013-08-02 23:55:06 +02:00
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trait HasTileLinkData extends TileLinkSubBundle {
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val data = Bits(width = conf.dataBits)
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2012-10-16 23:26:33 +02:00
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}
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2013-03-20 22:10:16 +01:00
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trait SourcedMessage extends Bundle
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trait ClientSourcedMessage extends SourcedMessage
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trait MasterSourcedMessage extends SourcedMessage
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2013-01-22 02:17:26 +01:00
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object Acquire
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2012-10-16 23:26:33 +02:00
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{
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2013-08-13 08:15:54 +02:00
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def apply(a_type: Bits, addr: UInt, client_xact_id: UInt)(implicit conf: TileLinkConfiguration): Acquire = {
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2013-01-22 02:17:26 +01:00
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val acq = new Acquire
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acq.a_type := a_type
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acq.addr := addr
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acq.client_xact_id := client_xact_id
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2013-08-02 23:55:06 +02:00
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acq.write_mask := Bits(0)
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acq.subword_addr := Bits(0)
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acq.atomic_opcode := Bits(0)
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2013-01-22 02:17:26 +01:00
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acq
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2012-10-16 23:26:33 +02:00
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}
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2013-08-13 08:15:54 +02:00
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def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, write_mask: Bits)(implicit conf: TileLinkConfiguration): Acquire = {
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val acq = apply(a_type, addr, client_xact_id)
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2013-01-22 02:17:26 +01:00
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acq.write_mask := write_mask
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acq
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2012-10-16 23:26:33 +02:00
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}
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2013-08-13 08:15:54 +02:00
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def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, subword_addr: UInt, atomic_opcode: UInt)(implicit conf: TileLinkConfiguration): Acquire = {
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val acq = apply(a_type, addr, client_xact_id)
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2013-01-22 02:17:26 +01:00
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acq.subword_addr := subword_addr
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acq.atomic_opcode := atomic_opcode
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acq
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2012-10-16 23:26:33 +02:00
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}
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}
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2013-08-02 23:55:06 +02:00
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class Acquire(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId {
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2013-08-12 19:36:44 +02:00
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val a_type = Bits(width = conf.co.acquireTypeWidth)
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2013-08-02 23:55:06 +02:00
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val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS)
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val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS)
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val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS)
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}
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2012-10-16 23:26:33 +02:00
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2013-08-13 08:15:54 +02:00
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class AcquireData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData
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2013-08-02 23:55:06 +02:00
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class Probe(implicit val conf: TileLinkConfiguration) extends MasterSourcedMessage with HasPhysicalAddress with HasMasterTransactionId {
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2013-08-12 19:36:44 +02:00
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val p_type = Bits(width = conf.co.probeTypeWidth)
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2012-10-16 23:26:33 +02:00
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}
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2013-01-29 01:39:45 +01:00
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object Release
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{
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2013-08-12 19:36:44 +02:00
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def apply(r_type: Bits, addr: UInt, client_xact_id: UInt, master_xact_id: UInt)(implicit conf: TileLinkConfiguration) = {
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2013-01-29 01:39:45 +01:00
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val rel = new Release
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rel.r_type := r_type
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rel.addr := addr
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rel.client_xact_id := client_xact_id
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rel.master_xact_id := master_xact_id
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rel
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}
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}
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2013-08-02 23:55:06 +02:00
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class Release(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId with HasMasterTransactionId {
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2013-08-12 19:36:44 +02:00
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val r_type = Bits(width = conf.co.releaseTypeWidth)
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2012-10-16 23:26:33 +02:00
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}
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2013-08-13 08:15:54 +02:00
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class ReleaseData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData
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2013-08-02 23:55:06 +02:00
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class Grant(implicit val conf: TileLinkConfiguration) extends MasterSourcedMessage with HasTileLinkData with HasClientTransactionId with HasMasterTransactionId {
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2013-08-12 19:36:44 +02:00
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val g_type = Bits(width = conf.co.grantTypeWidth)
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2012-10-16 23:26:33 +02:00
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}
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2013-08-13 08:15:54 +02:00
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class GrantAck(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
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2012-10-16 23:26:33 +02:00
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2013-05-22 02:19:07 +02:00
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trait DirectionalIO
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trait ClientSourcedIO extends DirectionalIO
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trait MasterSourcedIO extends DirectionalIO
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2013-09-11 01:15:41 +02:00
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class ClientSourcedFIFOIO[T <: Data](dType: T) extends DecoupledIO(dType) with ClientSourcedIO {
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override def clone = { new ClientSourcedFIFOIO(dType).asInstanceOf[this.type] }
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2013-05-22 02:19:07 +02:00
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}
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2013-09-11 01:15:41 +02:00
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class ClientSourcedDataIO[M <: Data, D <: Data](mType: M, dType: D) extends PairedDataIO(mType, dType) with ClientSourcedIO {
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override def clone = { new ClientSourcedDataIO(mType, dType).asInstanceOf[this.type] }
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2013-05-22 02:19:07 +02:00
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}
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2013-09-11 01:15:41 +02:00
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class MasterSourcedFIFOIO[T <: Data](dType: T) extends DecoupledIO(dType) with MasterSourcedIO {
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2013-05-22 02:19:07 +02:00
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flip()
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2013-09-11 01:15:41 +02:00
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override def clone = { new MasterSourcedFIFOIO(dType).asInstanceOf[this.type] }
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2013-05-22 02:19:07 +02:00
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}
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2013-09-11 01:15:41 +02:00
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class MasterSourcedDataIO[M <: Data, D <: Data](mType: M, dType: D) extends PairedDataIO(mType, dType) with MasterSourcedIO {
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2013-05-22 02:19:07 +02:00
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flip()
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2013-09-11 01:15:41 +02:00
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override def clone = { new MasterSourcedDataIO(mType, dType).asInstanceOf[this.type] }
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2013-05-22 02:19:07 +02:00
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}
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2013-01-22 02:17:26 +01:00
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2013-08-02 23:55:06 +02:00
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class UncachedTileLinkIO(implicit conf: TileLinkConfiguration) extends Bundle {
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implicit val ln = conf.ln
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2013-09-11 01:15:41 +02:00
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val acquire = new ClientSourcedDataIO(new LogicalNetworkIO(new Acquire), new LogicalNetworkIO(new AcquireData))
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val grant = new MasterSourcedFIFOIO(new LogicalNetworkIO(new Grant))
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val grant_ack = new ClientSourcedFIFOIO(new LogicalNetworkIO(new GrantAck))
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2013-03-20 22:10:16 +01:00
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override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] }
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}
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2013-08-02 23:55:06 +02:00
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class TileLinkIO(implicit conf: TileLinkConfiguration) extends UncachedTileLinkIO()(conf) {
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2013-09-11 01:15:41 +02:00
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val probe = new MasterSourcedFIFOIO(new LogicalNetworkIO(new Probe))
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val release = new ClientSourcedDataIO(new LogicalNetworkIO(new Release), new LogicalNetworkIO(new ReleaseData))
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2013-01-22 02:17:26 +01:00
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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2012-10-16 23:26:33 +02:00
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}
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2013-03-20 22:10:16 +01:00
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2013-08-13 09:01:11 +02:00
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abstract class UncachedTileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfiguration) extends Module {
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2013-07-10 00:37:42 +02:00
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def acquireClientXactId(in: Acquire, id: Int): Bits
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def grantClientXactId(in: Grant): Bits
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2013-08-12 19:36:44 +02:00
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def arbIdx(in: Grant): UInt
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2013-07-10 00:37:42 +02:00
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2013-08-02 23:55:06 +02:00
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implicit val (ln, co) = (conf.ln, conf.co)
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2013-03-20 22:10:16 +01:00
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val io = new Bundle {
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2013-08-12 19:36:44 +02:00
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val in = Vec.fill(n){new UncachedTileLinkIO}.flip
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2013-03-20 22:10:16 +01:00
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val out = new UncachedTileLinkIO
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}
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2013-07-10 00:37:42 +02:00
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def acqHasData(acq: LogicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
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2013-09-11 01:15:41 +02:00
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val acq_arb = Module(new PairedLockingRRArbiter(new LogicalNetworkIO(new Acquire), new LogicalNetworkIO(new AcquireData), n, REFILL_CYCLES, acqHasData _))
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2013-07-10 00:37:42 +02:00
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io.out.acquire <> acq_arb.io.out
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io.in.map(_.acquire).zipWithIndex.zip(acq_arb.io.in).map{ case ((req,id), arb) => {
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arb.data <> req.data
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arb.meta.valid := req.meta.valid
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arb.meta.bits := req.meta.bits
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arb.meta.bits.payload.client_xact_id := acquireClientXactId(req.meta.bits.payload, id)
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req.meta.ready := arb.meta.ready
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}}
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2013-09-11 01:15:41 +02:00
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val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
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2013-07-10 00:37:42 +02:00
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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2013-03-20 22:10:16 +01:00
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2013-07-10 00:37:42 +02:00
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io.out.grant.ready := Bool(false)
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for (i <- 0 until n) {
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io.in(i).grant.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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when (arbIdx(io.out.grant.bits.payload) === UInt(i)) {
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2013-07-10 00:37:42 +02:00
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io.in(i).grant.valid := io.out.grant.valid
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io.out.grant.ready := io.in(i).grant.ready
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}
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io.in(i).grant.bits := io.out.grant.bits
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io.in(i).grant.bits.payload.client_xact_id := grantClientXactId(io.out.grant.bits.payload)
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}
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}
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2013-08-13 09:01:11 +02:00
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class UncachedTileLinkIOArbiterThatAppendsArbiterId(n: Int)(implicit conf: TileLinkConfiguration) extends UncachedTileLinkIOArbiter(n)(conf) {
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def acquireClientXactId(in: Acquire, id: Int) = Cat(in.client_xact_id, UInt(id, log2Up(n)))
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def grantClientXactId(in: Grant) = in.client_xact_id >> UInt(log2Up(n))
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def arbIdx(in: Grant) = in.client_xact_id(log2Up(n)-1,0).toUInt
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}
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class UncachedTileLinkIOArbiterThatPassesId(n: Int)(implicit conf: TileLinkConfiguration) extends UncachedTileLinkIOArbiter(n)(conf) {
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2013-07-10 00:37:42 +02:00
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def acquireClientXactId(in: Acquire, id: Int) = in.client_xact_id
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def grantClientXactId(in: Grant) = in.client_xact_id
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2013-08-12 19:36:44 +02:00
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def arbIdx(in: Grant): UInt = in.client_xact_id
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2013-03-20 22:10:16 +01:00
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}
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2013-07-10 00:37:42 +02:00
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2013-08-13 09:01:11 +02:00
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class UncachedTileLinkIOArbiterThatUsesNewId(n: Int)(implicit conf: TileLinkConfiguration) extends UncachedTileLinkIOArbiter(n)(conf) {
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2013-08-12 19:36:44 +02:00
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def acquireClientXactId(in: Acquire, id: Int) = UInt(id, log2Up(n))
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def grantClientXactId(in: Grant) = UInt(0) // DNC
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2013-07-10 00:37:42 +02:00
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def arbIdx(in: Grant) = in.client_xact_id
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}
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