2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-01 05:26:55 +02:00
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package rocketchip
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2012-10-09 22:05:56 +02:00
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import Chisel._
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2015-07-30 02:56:19 +02:00
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import junctions._
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2012-10-09 22:05:56 +02:00
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import uncore._
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import rocket._
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2013-01-25 08:56:45 +01:00
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import rocket.Util._
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2012-10-09 22:05:56 +02:00
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2015-06-26 08:17:35 +02:00
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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/** Number of tiles */
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2014-08-08 21:27:47 +02:00
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case object NTiles extends Field[Int]
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2015-06-26 08:17:35 +02:00
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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2014-08-08 21:27:47 +02:00
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case object BankIdLSB extends Field[Int]
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2015-06-26 08:17:35 +02:00
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Whether to use the slow backup memory port [VLSI] */
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2014-08-25 04:30:53 +02:00
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case object UseBackupMemoryPort extends Field[Boolean]
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2015-06-26 08:17:35 +02:00
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/** Function for building some kind of coherence manager agent */
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2015-10-06 19:47:38 +02:00
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case object BuildL2CoherenceManager extends Field[Parameters => CoherenceAgent]
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2015-06-26 08:17:35 +02:00
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/** Function for building some kind of tile connected to a reset signal */
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2015-10-06 19:47:38 +02:00
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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2015-08-06 21:51:18 +02:00
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/** Start address of the "io" region in the memory map */
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case object ExternalIOStart extends Field[BigInt]
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2015-06-26 08:17:35 +02:00
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/** Utility trait for quick access to some relevant parameters */
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2015-10-06 19:47:38 +02:00
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trait HasTopLevelParameters extends HasHtifParameters {
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2015-10-02 23:23:42 +02:00
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lazy val nTiles = p(NTiles)
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2015-10-06 19:47:38 +02:00
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lazy val htifW = w
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lazy val csrAddrBits = 12
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2015-10-02 23:23:42 +02:00
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val nBanks = nMemChannels*nBanksPerMemChannel
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lazy val lsb = p(BankIdLSB)
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lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
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lazy val mifAddrBits = p(MIFAddrBits)
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lazy val mifDataBeats = p(MIFDataBeats)
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lazy val xLen = p(XLen)
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//require(lsb + log2Up(nBanks) < mifAddrBits)
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2014-08-25 04:30:53 +02:00
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}
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2014-09-24 22:08:45 +02:00
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2015-06-26 08:17:35 +02:00
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class MemBackupCtrlIO extends Bundle {
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val en = Bool(INPUT)
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val in_valid = Bool(INPUT)
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val out_ready = Bool(INPUT)
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val out_valid = Bool(OUTPUT)
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}
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2012-10-09 22:05:56 +02:00
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2015-06-26 08:17:35 +02:00
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/** Top-level io for the chip */
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2015-10-06 19:47:38 +02:00
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters {
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2015-06-26 08:17:35 +02:00
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val host = new HostIO
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val mem_backup_ctrl = new MemBackupCtrlIO
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}
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2012-10-09 22:05:56 +02:00
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2015-10-06 19:47:38 +02:00
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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2015-06-26 08:17:35 +02:00
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val mem = new MemIO
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}
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2015-10-06 19:47:38 +02:00
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class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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2015-10-02 23:23:42 +02:00
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val mem = Vec(new NastiIO, nMemChannels)
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val mmio = new NastiIO
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2015-06-26 08:17:35 +02:00
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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2015-10-06 19:47:38 +02:00
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class Top extends Module with HasTopLevelParameters {
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2015-10-02 23:23:42 +02:00
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implicit val p = params
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2015-06-26 08:17:35 +02:00
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val io = new TopIO
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2015-10-02 23:23:42 +02:00
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if(!p(UseZscale)) {
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2015-07-14 00:46:42 +02:00
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val temp = Module(new MultiChannelTop)
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2015-10-02 23:23:42 +02:00
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val arb = Module(new NastiArbiter(nMemChannels))
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val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
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2015-08-06 21:51:18 +02:00
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arb.io.master <> temp.io.mem
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conv.io.nasti <> arb.io.slave
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io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
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io.mem.req_data <> Queue(conv.io.mem.req_data, mifDataBeats)
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conv.io.mem.resp <> Queue(io.mem.resp, mifDataBeats)
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2015-07-14 00:46:42 +02:00
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io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
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io.host <> temp.io.host
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2015-08-06 21:51:18 +02:00
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// tie off the mmio port
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2015-10-02 23:23:42 +02:00
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val errslave = Module(new NastiErrorSlave)
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2015-08-06 21:51:18 +02:00
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errslave.io <> temp.io.mmio
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2015-07-14 00:46:42 +02:00
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} else {
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val temp = Module(new ZscaleTop)
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io.host <> temp.io.host
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}
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2015-06-26 08:17:35 +02:00
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}
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2015-10-06 19:47:38 +02:00
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class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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2015-06-26 08:17:35 +02:00
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val io = new MultiChannelTopIO
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// Build an Uncore and a set of Tiles
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2015-10-02 23:23:42 +02:00
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val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
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2015-10-06 19:47:38 +02:00
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val uncore = Module(new Uncore()(innerTLParams))
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val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
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2015-06-26 08:17:35 +02:00
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// Connect each tile to the HTIF
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uncore.io.htif.zip(tileList).zipWithIndex.foreach {
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case ((hl, tile), i) =>
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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2015-10-06 19:47:38 +02:00
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tile.io.host.csr.req <> Queue(hl.csr.req)
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hl.csr.resp <> Queue(tile.io.host.csr.resp)
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2015-06-26 08:17:35 +02:00
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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2015-10-06 19:47:38 +02:00
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hl.debug_stats_csr := tile.io.host.debug_stats_csr
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2014-08-25 04:30:53 +02:00
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}
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2015-06-26 08:17:35 +02:00
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached)
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
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2015-08-04 03:54:56 +02:00
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io.host <> uncore.io.host
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io.mem <> uncore.io.mem
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2015-08-06 21:51:18 +02:00
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io.mmio <> uncore.io.mmio
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2015-10-02 23:23:42 +02:00
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if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
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2012-10-09 22:05:56 +02:00
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}
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2015-06-26 08:17:35 +02:00
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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* Contains the Host-Target InterFace module (HTIF).
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*/
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2015-10-06 19:47:38 +02:00
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class Uncore(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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2012-10-09 22:05:56 +02:00
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val io = new Bundle {
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2014-08-25 04:30:53 +02:00
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val host = new HostIO
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2015-10-02 23:23:42 +02:00
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val mem = Vec(new NastiIO, nMemChannels)
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2015-09-20 22:43:39 +02:00
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val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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2015-10-06 19:47:38 +02:00
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val htif = Vec(new HtifIO, nTiles).flip
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2015-06-26 08:17:35 +02:00
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val mem_backup_ctrl = new MemBackupCtrlIO
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2015-10-02 23:23:42 +02:00
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val mmio = new NastiIO
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2013-04-23 02:38:13 +02:00
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}
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2015-10-06 19:47:38 +02:00
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val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
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2014-08-25 04:30:53 +02:00
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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2015-06-26 08:17:35 +02:00
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outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
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outmemsys.io.htif_uncached <> htif.io.mem
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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2013-09-25 10:21:41 +02:00
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2015-08-06 21:51:18 +02:00
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for (i <- 0 until nTiles) {
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io.htif(i).reset := htif.io.cpu(i).reset
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io.htif(i).id := htif.io.cpu(i).id
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htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
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io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
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2015-10-06 19:47:38 +02:00
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htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
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2015-08-06 21:51:18 +02:00
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2015-10-06 19:47:38 +02:00
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val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
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csr_arb.io.in(0) <> htif.io.cpu(i).csr
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csr_arb.io.in(1) <> outmemsys.io.csr(i)
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io.htif(i).csr <> csr_arb.io.out
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2015-08-06 21:51:18 +02:00
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}
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// Arbitrate SCR access between MMIO and HTIF
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val scrFile = Module(new SCRFile)
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2015-10-06 19:47:38 +02:00
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val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
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2015-08-06 21:51:18 +02:00
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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scrFile.io.smi <> scrArb.io.out
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// scrFile.io.scr <> (... your SCR connections ...)
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2014-08-25 04:30:53 +02:00
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// Wire the htif to the memory port(s) and host interface
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2015-10-06 19:47:38 +02:00
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io.host.debug_stats_csr := htif.io.host.debug_stats_csr
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2015-08-04 03:54:56 +02:00
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io.mem <> outmemsys.io.mem
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2015-08-06 21:51:18 +02:00
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io.mmio <> outmemsys.io.mmio
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2015-10-02 23:23:42 +02:00
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if(p(UseBackupMemoryPort)) {
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2015-06-26 08:17:35 +02:00
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outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
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2015-08-06 21:51:18 +02:00
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
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outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
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2014-08-25 04:30:53 +02:00
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} else {
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htif.io.host.out <> io.host.out
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htif.io.host.in <> io.host.in
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}
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2012-10-09 22:05:56 +02:00
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}
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2015-06-26 08:17:35 +02:00
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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2015-10-06 19:47:38 +02:00
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class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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2015-06-26 08:17:35 +02:00
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val io = new Bundle {
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2015-09-20 22:43:39 +02:00
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val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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2015-06-26 08:17:35 +02:00
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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2015-09-20 22:43:39 +02:00
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val incoherent = Vec(Bool(), nTiles).asInput
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2015-10-02 23:23:42 +02:00
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val mem = Vec(new NastiIO, nMemChannels)
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2015-06-26 08:17:35 +02:00
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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2015-10-06 19:47:38 +02:00
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val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
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2015-09-25 21:13:22 +02:00
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val scr = new SMIIO(xLen, scrAddrBits)
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2015-10-02 23:23:42 +02:00
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val mmio = new NastiIO
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2012-10-09 22:05:56 +02:00
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}
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2015-06-26 08:17:35 +02:00
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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val ordered_clients = (io.tiles_cached ++ (io.tiles_uncached :+ io.htif_uncached).map(TileLinkIOWrapper(_)))
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: Bits): UInt = if(nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0)
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val preBuffering = TileLinkDepths(2,2,2,2,2)
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val postBuffering = TileLinkDepths(0,0,1,0,0) //TODO: had EOS24 crit path on inner.release
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val l1tol2net = Module(
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if(nBanks == 1) new RocketChipTileLinkArbiter(sharerToClientId, preBuffering, postBuffering)
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else new RocketChipTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering, postBuffering))
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// Create point(s) of coherence serialization
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2015-08-06 21:51:18 +02:00
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val nManagers = nMemChannels * nBanksPerMemChannel
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2015-10-06 19:47:38 +02:00
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val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)(p)}
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2015-08-06 21:51:18 +02:00
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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2015-06-26 08:17:35 +02:00
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients <> ordered_clients
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2015-08-06 21:51:18 +02:00
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
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2015-06-26 08:17:35 +02:00
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// Create a converter between TileLinkIO and MemIO for each channel
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2015-10-02 23:23:42 +02:00
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val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
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2015-06-26 08:17:35 +02:00
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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2015-08-06 21:51:18 +02:00
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2015-10-02 23:23:42 +02:00
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val addrMap = new AddrHashMap(p(NastiAddrMap))
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val nMasters = managerEndpoints.size + 1
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val nSlaves = addrMap.nEntries
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2015-08-06 21:51:18 +02:00
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println("Generated Address Map")
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for ((name, base, size, _) <- addrMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + size - 1}%x")
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2015-06-26 08:17:35 +02:00
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}
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2014-08-25 04:30:53 +02:00
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2015-10-02 23:23:42 +02:00
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val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
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2015-08-06 21:51:18 +02:00
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for ((bank, i) <- managerEndpoints.zipWithIndex) {
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2015-10-06 19:47:38 +02:00
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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val conv = Module(new NastiIOTileLinkIOConverter()(outerTLParams))
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2015-08-06 21:51:18 +02:00
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unwrap.io.in <> bank.outerTL
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conv.io.tl <> unwrap.io.out
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interconnect.io.masters(i) <> conv.io.nasti
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}
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val rtc = Module(new RTC(CSRs.mtime))
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|
|
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interconnect.io.masters(nManagers) <> rtc.io
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|
|
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|
|
|
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for (i <- 0 until nTiles) {
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|
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val csrName = s"conf:csr$i"
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|
|
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val csrPort = addrMap(csrName).port
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2015-10-06 19:47:38 +02:00
|
|
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val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
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2015-08-06 21:51:18 +02:00
|
|
|
conv.io.nasti <> interconnect.io.slaves(csrPort)
|
2015-10-06 19:47:38 +02:00
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io.csr(i) <> conv.io.smi
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2015-08-06 21:51:18 +02:00
|
|
|
}
|
|
|
|
|
2015-10-06 19:47:38 +02:00
|
|
|
val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
|
2015-08-06 21:51:18 +02:00
|
|
|
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
|
|
|
|
io.scr <> conv.io.smi
|
|
|
|
|
|
|
|
io.mmio <> interconnect.io.slaves(addrMap("io").port)
|
|
|
|
|
|
|
|
val mem_channels = interconnect.io.slaves.take(nMemChannels)
|
|
|
|
|
2015-06-26 08:17:35 +02:00
|
|
|
// Create a SerDes for backup memory port
|
2015-10-02 23:23:42 +02:00
|
|
|
if(p(UseBackupMemoryPort)) {
|
2015-08-06 21:51:18 +02:00
|
|
|
VLSIUtils.doOuterMemorySystemSerdes(
|
|
|
|
mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
|
2015-10-06 19:47:38 +02:00
|
|
|
nMemChannels, htifW, p(CacheBlockOffsetBits))
|
2015-06-26 08:17:35 +02:00
|
|
|
} else { io.mem <> mem_channels }
|
2012-10-09 22:05:56 +02:00
|
|
|
}
|