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e9625bf8ee
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Add initial ML507Shell stub based on VC707Shell
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2018-04-12 00:42:46 +02:00 |
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Wesley W. Terpstra
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8519ba8d4e
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vc707: setup 100MHz PLL
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2018-02-08 07:21:45 -08:00 |
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Henry Styles
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61ece0bf00
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VC707 Shell : additional skewed clocks
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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33c88b8cc4
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Move Xilinx unisims into separate file
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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e1bfb75188
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
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2017-11-01 14:23:07 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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