295 lines
8.9 KiB
Scala
295 lines
8.9 KiB
Scala
// See LICENSE for license details.
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package sifive.fpgashells.ip.xilinx
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import Chisel._
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import chisel3.core.{Input, Output, attach}
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import chisel3.experimental.{Analog}
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import freechips.rocketchip.util.{ElaborationArtefacts}
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import sifive.blocks.devices.pinctrl.{BasePin}
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//========================================================================
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// This file contains common devices used by our Xilinx FPGA flows and some
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// BlackBox modules used in the Xilinx FPGA flows
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//========================================================================
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//-------------------------------------------------------------------------
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// IBUFDS
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//-------------------------------------------------------------------------
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//IP : xilinx unisim IBUFDS. SelectIO Differential Signaling Input
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// Buffer unparameterized
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class IBUFDS extends BlackBox {
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val io = new Bundle {
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val O = Bool(OUTPUT)
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val I = Bool(INPUT)
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val IB = Bool(INPUT)
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}
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}
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//-------------------------------------------------------------------------
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// IBUFG
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//-------------------------------------------------------------------------
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/** IBUFG -- Clock Input Buffer */
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class IBUFG extends BlackBox {
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val io = new Bundle {
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val O = Output(Clock())
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val I = Input(Clock())
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}
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}
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object IBUFG {
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def apply (pin: Clock): Clock = {
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val pad = Module (new IBUFG())
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pad.io.I := pin
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pad.io.O
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}
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}
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//-------------------------------------------------------------------------
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// IOBUF
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//-------------------------------------------------------------------------
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/** IOBUF -- Bidirectional IO Buffer. */
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class IOBUF extends BlackBox {
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val io = new Bundle {
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val O = Output(Bool())
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val IO = Analog(1.W)
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val I = Input(Bool())
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val T = Input(Bool())
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}
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}
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object IOBUF {
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def apply (pin: Analog, ctrl: BasePin): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := ctrl.o.oval
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pad.io.T := ~ctrl.o.oe
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ctrl.i.ival := pad.io.O & ctrl.o.ie
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attach(pad.io.IO, pin)
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pad.io.O & ctrl.o.ie
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}
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// Creates an output IOBUF
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def apply (pin: Analog, in: Bool): Unit = {
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val pad = Module(new IOBUF())
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pad.io.I := in
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pad.io.T := false.B
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attach(pad.io.IO, pin)
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}
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// Creates an input IOBUF
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def apply (pin: Analog): Bool = {
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val pad = Module(new IOBUF())
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pad.io.I := false.B
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pad.io.T := true.B
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attach(pad.io.IO, pin)
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pad.io.O
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}
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}
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//-------------------------------------------------------------------------
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// PULLUP
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//-------------------------------------------------------------------------
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/** PULLUP : can be applied to Input to add a Pullup. */
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class PULLUP extends BlackBox {
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val io = new Bundle {
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val O = Analog(1.W)
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}
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}
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object PULLUP {
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def apply (pin: Analog): Unit = {
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val pullup = Module(new PULLUP())
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attach(pullup.io.O, pin)
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}
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}
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//-------------------------------------------------------------------------
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// mmcm
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//-------------------------------------------------------------------------
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/** mmcm: This is generated by the Xilinx IP Generation Scripts */
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class mmcm extends BlackBox {
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val io = new Bundle {
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val clk_in1 = Input(Clock())
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val clk_out1 = Output(Clock())
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val clk_out2 = Output(Clock())
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val clk_out3 = Output(Clock())
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val resetn = Input(Bool())
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val locked = Output(Bool())
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}
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}
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//-------------------------------------------------------------------------
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// reset_sys
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//-------------------------------------------------------------------------
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/** reset_sys: This is generated by the Xilinx IP Generation Scripts */
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class reset_sys extends BlackBox {
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val io = new Bundle {
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val slowest_sync_clk = Input(Clock())
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val ext_reset_in = Input(Bool())
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val aux_reset_in = Input(Bool())
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val mb_debug_sys_rst = Input(Bool())
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val dcm_locked = Input(Bool())
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val mb_reset = Output(Bool())
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val bus_struct_reset = Output(Bool())
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val peripheral_reset = Output(Bool())
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val interconnect_aresetn = Output(Bool())
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val peripheral_aresetn = Output(Bool())
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}
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}
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//-------------------------------------------------------------------------
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// reset_mig
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//-------------------------------------------------------------------------
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/** reset_mig: This is generated by the Xilinx IP Generation Scripts */
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class reset_mig extends BlackBox {
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val io = new Bundle {
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val slowest_sync_clk = Input(Clock())
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val ext_reset_in = Input(Bool())
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val aux_reset_in = Input(Bool())
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val mb_debug_sys_rst = Input(Bool())
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val dcm_locked = Input(Bool())
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val mb_reset = Output(Bool())
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val bus_struct_reset = Output(Bool())
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val peripheral_reset = Output(Bool())
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val interconnect_aresetn = Output(Bool())
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val peripheral_aresetn = Output(Bool())
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}
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}
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//-------------------------------------------------------------------------
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// PowerOnResetFPGAOnly
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//-------------------------------------------------------------------------
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/** PowerOnResetFPGAOnly -- this generates a power_on_reset signal using
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* initial blocks. It is synthesizable on FPGA flows only.
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*/
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// This is a FPGA-Only construct, which uses
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// 'initial' constructions
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class PowerOnResetFPGAOnly extends BlackBox {
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val io = new Bundle {
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val clock = Input(Clock())
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val power_on_reset = Output(Bool())
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}
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}
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object PowerOnResetFPGAOnly {
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def apply (clk: Clock): Bool = {
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val por = Module(new PowerOnResetFPGAOnly())
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por.io.clock := clk
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por.io.power_on_reset
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}
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}
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//-------------------------------------------------------------------------
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// vc707clk_wiz_sync
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//-------------------------------------------------------------------------
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//IP : xilinx mmcm with "NO_BUFFER" input clock
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class vc707clk_wiz_sync extends BlackBox {
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val io = new Bundle {
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val clk_in1 = Bool(INPUT)
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val clk_out1 = Clock(OUTPUT)
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val clk_out2 = Clock(OUTPUT)
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val clk_out3 = Clock(OUTPUT)
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val clk_out4 = Clock(OUTPUT)
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val clk_out5 = Clock(OUTPUT)
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val clk_out6 = Clock(OUTPUT)
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val clk_out7 = Clock(OUTPUT)
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val reset = Bool(INPUT)
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val locked = Bool(OUTPUT)
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}
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ElaborationArtefacts.add(
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"vc707clk_wiz_sync.vivado.tcl",
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"""create_ip -name clk_wiz -vendor xilinx.com -library ip -version 5.3 -module_name vc707clk_wiz_sync -dir $ipdir -force
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set_property -dict [list \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_SOURCE {No_buffer} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.CLKOUT4_USED {true} \
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CONFIG.CLKOUT5_USED {true} \
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CONFIG.CLKOUT6_USED {true} \
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CONFIG.CLKOUT7_USED {true} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {37.5} \
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CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \
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CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \
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CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \
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CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {75} \
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CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
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CONFIG.PRIM_IN_FREQ {200.000} \
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CONFIG.CLKIN1_JITTER_PS {50.0} \
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CONFIG.MMCM_DIVCLK_DIVIDE {1} \
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CONFIG.MMCM_CLKFBOUT_MULT_F {4.500} \
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CONFIG.MMCM_CLKIN1_PERIOD {5.0} \
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CONFIG.MMCM_CLKOUT0_DIVIDE_F {72.000} \
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CONFIG.MMCM_CLKOUT1_DIVIDE {36} \
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CONFIG.MMCM_CLKOUT2_DIVIDE {24} \
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CONFIG.MMCM_CLKOUT3_DIVIDE {18} \
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CONFIG.MMCM_CLKOUT4_DIVIDE {9} \
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CONFIG.MMCM_CLKOUT5_DIVIDE {6} \
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CONFIG.MMCM_CLKOUT6_DIVIDE {12} \
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CONFIG.NUM_OUT_CLKS {7} \
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CONFIG.CLKOUT1_JITTER {168.247} \
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CONFIG.CLKOUT1_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT2_JITTER {146.624} \
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CONFIG.CLKOUT2_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT3_JITTER {135.178} \
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CONFIG.CLKOUT3_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT4_JITTER {127.364} \
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CONFIG.CLKOUT4_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT5_JITTER {110.629} \
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CONFIG.CLKOUT5_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT6_JITTER {102.207} \
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CONFIG.CLKOUT6_PHASE_ERROR {91.235} \
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CONFIG.CLKOUT7_JITTER {117.249} \
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CONFIG.CLKOUT7_PHASE_ERROR {91.235}] [get_ips vc707clk_wiz_sync] """
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)
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}
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//-------------------------------------------------------------------------
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// vc707reset
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//-------------------------------------------------------------------------
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class vc707reset() extends BlackBox
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{
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val io = new Bundle{
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val areset = Bool(INPUT)
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val clock1 = Clock(INPUT)
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val reset1 = Bool(OUTPUT)
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val clock2 = Clock(INPUT)
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val reset2 = Bool(OUTPUT)
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val clock3 = Clock(INPUT)
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val reset3 = Bool(OUTPUT)
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val clock4 = Clock(INPUT)
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val reset4 = Bool(OUTPUT)
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}
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}
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//-------------------------------------------------------------------------
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// sdio_spi_bridge
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//-------------------------------------------------------------------------
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class sdio_spi_bridge() extends BlackBox
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{
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val io = new Bundle{
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val clk = Clock(INPUT)
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val reset = Bool(INPUT)
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val sd_cmd = Analog(1.W)
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val sd_dat = Analog(4.W)
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val spi_sck = Bool(INPUT)
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val spi_cs = Bool(INPUT)
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val spi_dq_o = Bits(INPUT,4)
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val spi_dq_i = Bits(OUTPUT,4)
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}
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}
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