Henry Styles
|
b7ee0ab0f0
|
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
|
2017-09-07 10:41:12 -07:00 |
|
Megan Wachs
|
cab572fab2
|
synchronizers: decided that ShiftRegInit should be reversed as the others.
|
2017-09-07 09:54:35 -07:00 |
|
Megan Wachs
|
fd70d118d3
|
synchronizers: Update constraints to match new hierarchy for synchronizers
|
2017-09-07 07:50:22 -07:00 |
|
Megan Wachs
|
13671f906d
|
synchronizers: Use new primitives
|
2017-09-06 11:00:25 -07:00 |
|
Shreesha Srinath
|
2389e6e957
|
Fix the package path for xilinx vc707mig
|
2017-08-18 14:47:03 -07:00 |
|
Shreesha Srinath
|
38afe2957f
|
Fixing typos in the tcl script
|
2017-08-18 11:34:35 -07:00 |
|
Shreesha Srinath
|
ae767458af
|
Pass debug hooks through project-specific makefiles
|
2017-08-18 11:27:02 -07:00 |
|
Shreesha Srinath
|
c58e79f155
|
vc707: Updates to the constraints and shell
|
2017-08-17 18:51:01 -07:00 |
|
Shreesha Srinath
|
ab8cf0775f
|
Initial commit for fpga-shells
|
2017-08-16 11:23:45 -07:00 |
|