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Commit Graph

16 Commits

Author SHA1 Message Date
Henry Styles
045b290fbd VC707 JTAG support throught XM105 FMC or reuse of LCD header 2018-02-08 07:21:44 -08:00
Henry Styles
f9dc552ddc Xilinx unisim typo 2018-02-08 07:21:44 -08:00
Henry Styles
33c88b8cc4 Move Xilinx unisims into separate file 2018-02-08 07:21:44 -08:00
Wesley W. Terpstra
8b0d7ec91a
TransferSizes: just because a device CAN do more does not mean it should (#15)
Capping TransferSizes at 128 fits nicely in 3 size bits.
2017-12-10 00:42:11 -08:00
Henry Styles
e1bfb75188 VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock 2017-11-01 14:23:07 -07:00
Wesley W. Terpstra
df8e6b8e8c
xilinxvc707pciex1: use new node-style API and abstract crossing (#13) 2017-10-28 12:27:24 -07:00
Wesley W. Terpstra
65ac5d4588 xilinxVC707mig: convert to the island pattern (#12) 2017-10-26 16:38:52 -07:00
Henry Styles
61b167e8d9 VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals 2017-10-23 16:53:59 -07:00
Wesley W. Terpstra
d8e50c7646 TLToAXI4: remove now unnecessary argument (#10) 2017-10-12 14:37:21 -07:00
Wesley W. Terpstra
4af0552374 diplomacy: update to new API (#7) 2017-09-27 16:32:43 -07:00
Megan Wachs
bf48e2c7c4 signal_bundles: Use the new way as .fromPorts is gone 2017-09-22 13:31:11 -07:00
Henry Styles
9f75e6eb59 Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
2017-09-08 15:52:53 -07:00
Megan Wachs
13671f906d synchronizers: Use new primitives 2017-09-06 11:00:25 -07:00
Shreesha Srinath
2389e6e957 Fix the package path for xilinx vc707mig 2017-08-18 14:47:03 -07:00
Shreesha Srinath
c58e79f155 vc707: Updates to the constraints and shell 2017-08-17 18:51:01 -07:00
Shreesha Srinath
ab8cf0775f Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00