Wesley W. Terpstra
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4386187016
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vc707: add clock groups dynamically iff they exist
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2018-02-25 14:33:32 -08:00 |
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Wesley W. Terpstra
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8519ba8d4e
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vc707: setup 100MHz PLL
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2018-02-08 07:21:45 -08:00 |
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Wesley W. Terpstra
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506d2da883
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vc707: update constraints to match correct mmcm
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2018-02-08 07:21:45 -08:00 |
Henry Styles
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045b290fbd
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VC707 JTAG support throught XM105 FMC or reuse of LCD header
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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e1bfb75188
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
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2017-11-01 14:23:07 -07:00 |
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Henry Styles
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dc6bb40d1b
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VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP
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2017-10-23 17:27:36 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
Megan Wachs
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31650a2d23
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Merge remote-tracking branch 'origin/master' into synchronizers
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2017-09-07 10:46:03 -07:00 |
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Henry Styles
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b7ee0ab0f0
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:41:12 -07:00 |
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Megan Wachs
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cab572fab2
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synchronizers: decided that ShiftRegInit should be reversed as the others.
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2017-09-07 09:54:35 -07:00 |
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Megan Wachs
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fd70d118d3
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synchronizers: Update constraints to match new hierarchy for synchronizers
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2017-09-07 07:50:22 -07:00 |
Shreesha Srinath
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c58e79f155
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vc707: Updates to the constraints and shell
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2017-08-17 18:51:01 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |