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Add top modules and pin constraints for the two ALU CPLDs

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This commit is contained in:
Klemens Schölhorn 2018-07-26 21:44:35 +02:00
parent 7202b01c93
commit 1116ec8a50
7 changed files with 170 additions and 24 deletions
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3
firmware/alu/.gitignore vendored
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@ -87,6 +87,7 @@ xilinxsim.ini
# cpld
/main_html/
*_html/
*.gyd
*.jed
*.mfd
@ -96,4 +97,6 @@ xilinxsim.ini
*.vm6
*.xml
*.err
*.tim
*.tspec

33
firmware/alu/CPLD1.ucf Normal file
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@ -0,0 +1,33 @@
NET "func(0)" LOC = "43";
NET "func(1)" LOC = "44";
NET "func(2)" LOC = "1";
NET "func(3)" LOC = "2";
NET "accu(0)" LOC = "27";
NET "accu(1)" LOC = "28";
NET "accu(2)" LOC = "29";
NET "accu(3)" LOC = "30";
NET "accu(4)" LOC = "31";
NET "accu(5)" LOC = "32";
NET "accu(6)" LOC = "37";
NET "accu(7)" LOC = "38";
NET "ram(0)" LOC = "39";
NET "ram(1)" LOC = "40";
NET "ram(2)" LOC = "41";
NET "ram(3)" LOC = "42";
NET "ram(4)" LOC = "5";
NET "ram(5)" LOC = "6";
NET "ram(6)" LOC = "7";
NET "ram(7)" LOC = "8";
NET "result(0)" LOC = "22";
NET "result(1)" LOC = "21";
NET "result(2)" LOC = "20";
NET "result(3)" LOC = "19";
NET "result(4)" LOC = "18";
NET "result(5)" LOC = "16";
NET "result(6)" LOC = "14";
NET "result(7)" LOC = "13";
NET "carry_out" LOC = "3";

30
firmware/alu/CPLD1.vhd Normal file
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@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all;
entity CPLD1 is
port (
func: in std_logic_vector(3 downto 0);
accu: in std_logic_vector(7 downto 0);
ram: in std_logic_vector(7 downto 0);
result: out std_logic_vector(7 downto 0);
carry_out: out std_logic
);
end CPLD1;
architecture rtl of CPLD1 is
begin
alu: entity work.alu generic map (
WIDTH => 8,
FIRST => true
) port map (
func => func,
accu => accu,
ram => ram,
carry_in => '0',
result => result,
carry_out => carry_out
);
end rtl;

33
firmware/alu/CPLD2.ucf Normal file
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@ -0,0 +1,33 @@
NET "func(0)" LOC = "44";
NET "func(1)" LOC = "43";
NET "func(2)" LOC = "42";
NET "func(3)" LOC = "41";
NET "accu(8)" LOC = "27";
NET "accu(9)" LOC = "28";
NET "accu(10)" LOC = "29";
NET "accu(11)" LOC = "30";
NET "accu(12)" LOC = "31";
NET "accu(13)" LOC = "32";
NET "accu(14)" LOC = "37";
NET "accu(15)" LOC = "38";
NET "ram(8)" LOC = "39";
NET "ram(9)" LOC = "40";
NET "ram(10)" LOC = "2";
NET "ram(11)" LOC = "3";
NET "ram(12)" LOC = "5";
NET "ram(13)" LOC = "6";
NET "ram(14)" LOC = "7";
NET "ram(15)" LOC = "8";
NET "result(8)" LOC = "21";
NET "result(9)" LOC = "20";
NET "result(10)" LOC = "19";
NET "result(11)" LOC = "18";
NET "result(12)" LOC = "16";
NET "result(13)" LOC = "14";
NET "result(14)" LOC = "13";
NET "result(15)" LOC = "12";
NET "carry_in" LOC = "33";

30
firmware/alu/CPLD2.vhd Normal file
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@ -0,0 +1,30 @@
library ieee;
use ieee.std_logic_1164.all;
entity CPLD2 is
port (
func: in std_logic_vector(3 downto 0);
accu: in std_logic_vector(15 downto 8);
ram: in std_logic_vector(15 downto 8);
carry_in: in std_logic;
result: out std_logic_vector(15 downto 8)
);
end CPLD2;
architecture rtl of CPLD2 is
begin
alu: entity work.alu generic map (
WIDTH => 8,
FIRST => false
) port map (
func => func,
accu => accu,
ram => ram,
carry_in => carry_in,
result => result,
carry_out => open
);
end rtl;

6
firmware/alu/main.vhd → firmware/alu/alu.vhd
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@ -3,7 +3,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
entity main is
entity alu is
generic (
WIDTH: integer := 8;
FIRST: boolean := true
@ -16,9 +16,9 @@ entity main is
result: out std_logic_vector(WIDTH-1 downto 0);
carry_out: out std_logic
);
end main;
end alu;
architecture rtl of main is
architecture rtl of alu is
signal x: std_logic_vector(WIDTH-1 downto 0);
signal y: std_logic_vector(WIDTH-1 downto 0);
signal cin: std_logic;

59
firmware/alu/alu.xise
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@ -15,10 +15,6 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
@ -29,7 +25,22 @@
</file>
<file xil_pn:name="tests/control_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="CPLD1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="CPLD2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="CPLD2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
@ -39,7 +50,7 @@
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@ -47,7 +58,9 @@
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -58,9 +71,9 @@
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc9572" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500 CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable FASTConnect/UIM optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
@ -84,11 +97,12 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="tests/control_logic.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CPLD2|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="CPLD2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CPLD2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -134,16 +148,16 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output File Name" xil_pn:value="CPLD2" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="control_logic_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="control_logic_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="control_logic_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="control_logic_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CPLD2_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CPLD2_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CPLD2_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CPLD2_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@ -179,9 +193,10 @@
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="CPLD1.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
@ -219,7 +234,7 @@
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
@ -233,7 +248,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/CPLD2" xil_pn:name="CPLD2.ucf"/>
</bindings>
<libraries/>