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@ -15,10 +15,6 @@
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="adder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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@ -29,7 +25,22 @@
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</file>
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<file xil_pn:name="tests/control_logic.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="CPLD1.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="CPLD2.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="CPLD2.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@ -39,7 +50,7 @@
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<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -47,7 +58,9 @@
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<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
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<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/>
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<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
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<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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@ -58,9 +71,9 @@
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<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc9572" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="XC9500 CPLDs" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
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<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable FASTConnect/UIM optimization" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -84,11 +97,12 @@
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<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
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<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
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<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
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<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="tests/control_logic.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CPLD2|rtl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="CPLD2.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CPLD2" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -134,16 +148,16 @@
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Output File Name" xil_pn:value="CPLD2" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
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<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="control_logic_map.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="control_logic_timesim.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="control_logic_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="control_logic_translate.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CPLD2_map.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="CPLD2_timesim.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CPLD2_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CPLD2_translate.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -179,9 +193,10 @@
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Target UCF File Name" xil_pn:value="CPLD1.ucf" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
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@ -219,7 +234,7 @@
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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@ -233,7 +248,9 @@
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings/>
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<bindings>
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<binding xil_pn:location="/CPLD2" xil_pn:name="CPLD2.ucf"/>
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</bindings>
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<libraries/>
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