31 lines
613 B
VHDL
31 lines
613 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity CPLD2 is
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port (
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func: in std_logic_vector(3 downto 0);
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accu: in std_logic_vector(15 downto 8);
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ram: in std_logic_vector(15 downto 8);
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carry_in: in std_logic;
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result: out std_logic_vector(15 downto 8)
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);
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end CPLD2;
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architecture rtl of CPLD2 is
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begin
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alu: entity work.alu generic map (
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WIDTH => 8,
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FIRST => false
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) port map (
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func => func,
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accu => accu,
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ram => ram,
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carry_in => carry_in,
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result => result,
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carry_out => open
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);
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end rtl;
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