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riscv/sifive-blocks
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7ac56c01afed8044ab73d648a51966a7198af2c6
sifive-blocks/src/main/scala/devices/spi
T
History
Megan Wachs fb4977b518 SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 09:54:56 -08:00
..
SPIArbiter.scala
spi: correct polarity of FIRRTL combo loop detection workaround.
2017-03-31 13:49:34 -07:00
SPIBundle.scala
spi: SPIParamsBase param needs to be public
2018-03-04 13:26:19 -08:00
SPIConsts.scala
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
SPIFIFO.scala
spi: Fix off-by-one error in calculating cycles per data frame
2017-05-02 12:35:34 -07:00
SPIFlash.scala
spi: Fix invalid D channel response when flash interface is disabled
2017-08-02 13:50:00 -07:00
SPIMedia.scala
devices: create periphery keys for all devices
2017-03-02 20:39:25 -08:00
SPIPeriphery.scala
periphery: bus api update (#50)
2018-03-01 01:15:02 -08:00
SPIPhysical.scala
shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
2017-09-06 10:59:07 -07:00
SPIPins.scala
SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 09:54:56 -08:00
SPIRegs.scala
Initial commit.
2016-11-29 04:08:44 -08:00
TLSPI.scala
sifive-blocks: update to new rocket API (#43)
2017-10-26 16:10:18 -07:00
TLSPIFlash.scala
diplomacy: update to new API (#40)
2017-09-27 16:33:18 -07:00
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