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riscv/sifive-blocks
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7ac56c01afed8044ab73d648a51966a7198af2c6
sifive-blocks/src/main/scala/devices
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Wesley W. Terpstra ac55313e8e msi: add a MSIMaster to bridge interrupts over ChipLink
2018-03-22 16:06:12 -07:00
..
chiplink
devices: add support for the chiplink protocol
2018-03-22 16:06:10 -07:00
gpio
Remove cloneTypes in favor of autoclonetype (#51)
2018-03-04 10:29:51 -08:00
i2c
Remove cloneTypes in favor of autoclonetype (#51)
2018-03-04 10:29:51 -08:00
jtag
pinctrl: Create extendable Signal classes
2017-09-22 13:17:31 -07:00
mockaon
periphery: bus api update (#50)
2018-03-01 01:15:02 -08:00
msi
msi: add a MSIMaster to bridge interrupts over ChipLink
2018-03-22 16:06:12 -07:00
pinctrl
pinctrl: Add the ability to convert EnhancedPin to BasePin
2017-10-06 13:43:23 -07:00
pwm
Remove cloneTypes in favor of autoclonetype (#51)
2018-03-04 10:29:51 -08:00
spi
SPI: Use the standard synchronizer primitive for the SPI DQ inputs
2018-03-07 09:54:56 -08:00
uart
Remove cloneTypes in favor of autoclonetype (#51)
2018-03-04 10:29:51 -08:00
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