riscv/sifive-blocks
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6795f401075e2d21166613ff2c1c3a585b2ff1e8
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113 Commits

Author SHA1 Message Date
Henry Cook
6795f40107 spi: SPIParamsBase param needs to be public 2018-03-04 13:26:19 -08:00
Jack Koenig
39287b9215 Remove cloneTypes in favor of autoclonetype (#51) 
* Remove cloneTypes in favor of autoclonetype

* Consistently use private val for autoclonetype
 2018-03-04 10:29:51 -08:00
Henry Cook
00fbfb6dd8 periphery: bus api update (#50) 2018-03-01 01:15:02 -08:00
solomatnikov
3dee152775 Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49) 2018-02-23 12:09:18 -08:00
Alex Solomatnikov
ef8139f18c Do not allow status read if status.transferInProgress is going to change next cycle 2018-02-22 18:43:39 -08:00
Megan Wachs
6c5b80671c i2c: Allow irq to be cleared 2018-02-16 16:34:10 -08:00
Albert Ou
14ffd35f5c uart: Eliminate systemic baud rate error with low divisor values 
This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.

Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit.  The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".

The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.
 2018-01-04 19:51:24 -08:00
Megan Wachs
9052a079d4 Merge pull request #46 from sifive/gpio_iof_pueds 
GPIO: IOF should not override PUE and DS
 2017-11-08 17:18:02 -08:00
Megan Wachs
90404980b8 GPIO: IOF should not override PUE and DS 2017-11-08 15:15:32 -08:00
Wesley W. Terpstra
d1d2f47f60 PMU: adapt to new chisel API (#45) 2017-11-02 15:44:02 -07:00
Wesley W. Terpstra
90e6ea1d2d devices: switch to using node-style API (#44) 2017-10-28 12:29:31 -07:00
Wesley W. Terpstra
e4960a4e5a sifive-blocks: update to new rocket API (#43) 2017-10-26 16:10:18 -07:00
Megan Wachs
94f8c1705d pinctrl: Add the ability to convert EnhancedPin to BasePin 2017-10-06 13:43:23 -07:00
Megan Wachs
3e47ed6b33 PWM: Add the ability to invert the output directly in PWM (without GPIO pinmux) 2017-10-02 15:08:06 -07:00
Wesley W. Terpstra
4fcf349adb diplomacy: update to new API (#40) 2017-09-27 16:33:18 -07:00
Megan Wachs
77df75f4ed GPIO Pins needs clone type. 2017-09-22 16:38:37 -07:00
Megan Wachs
5d1e9b793a signal_bundles: add missing file 2017-09-22 13:55:55 -07:00
Megan Wachs
81e301f9f7 pinctrl: Create extendable Signal classes 2017-09-22 13:17:31 -07:00
Megan Wachs
38f537c438 device pins: Create classes that can be something other than a Pin subclass 2017-09-20 16:43:42 -07:00
Megan Wachs
6a13639cf3 SPI: Make it easier to build arbitrary bundles 2017-09-20 16:21:21 -07:00
Henry Cook
f8dcfbacfa uart: use PeripheryBusKey (#38) 2017-09-15 14:54:10 -07:00
Megan Wachs
97c3fcb4b6 shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate 2017-09-06 10:59:07 -07:00
Megan Wachs
4381e395af i2c/uart: Name the synchronizers 2017-09-05 18:40:22 -07:00
Megan Wachs
48222bcd2d gpio: Use Synchronizer for the inputs 2017-09-05 18:35:09 -07:00
Megan Wachs
1feaefe4c5 i2c, uart: Use Synchronizer primitives for the inputs 2017-09-05 18:32:37 -07:00
Megan Wachs
c68d556768 ShiftRegInit: use the rocket-chip version since it is there now 2017-09-05 17:51:40 -07:00
Megan Wachs
7d07e3af0b regs: remove duplicate ShiftReg file which is now in rocket-chip 2017-09-05 17:33:32 -07:00
Megan Wachs
acb8889382 remove duplicate ResetCatchAndSync definition 2017-08-24 18:12:36 -07:00
Megan Wachs
70c25846b8 spi: Make memory mapped interface depth a parameter 2017-08-20 12:39:38 -07:00
Wesley W. Terpstra
a814cba04f spi: put a request buffer infront of SPI 
This will prevent SPI from blocking other pbus requests.
 2017-08-19 12:52:10 -07:00
Shreesha Srinath
249c23e617 Renamed ShiftReg to ShiftRegister 2017-08-17 18:22:51 -07:00
Shreesha Srinath
7035ccc431 Updates to go with the fpga-shells directory 2017-08-17 18:12:49 -07:00
Wesley W. Terpstra
d973c659eb uart: make it easy to simulate large text printouts (#33) 2017-08-10 16:32:48 -07:00
Shreesha Srinath
26dd0af657 mockaon: Adds logic to detect external rtc toggles 2017-08-02 18:11:05 -07:00
Albert Ou
c59356d1de spi: Fix invalid D channel response when flash interface is disabled 
Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.
 2017-08-02 13:50:00 -07:00
Henry Cook
015f87ec6b allow bundle content params to be specified via a def (#29) 2017-08-02 11:46:27 -07:00
Wesley W. Terpstra
fced2323bd spi: remove removed sink arg 2017-07-26 16:02:44 -07:00
Yunsup Lee
4cb2f8af17 mockaon: rename pads to pins 2017-07-25 15:02:22 -07:00
Megan Wachs
aa6d911c26 Ports: Rename the 'fromXYZPort' to 'fromPort' since it's redundant 2017-07-25 08:36:28 -07:00
Megan Wachs
2139ab0d98 Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-25 07:05:22 -07:00
Yunsup Lee
5e51e1e931 uart: use PeripheryBusParams.frequency to calculate default divisor (#28) 2017-07-25 00:56:22 -07:00
Megan Wachs
0a80d1987d Merge remote-tracking branch 'origin/master' into typed_pad_ctrl 2017-07-24 10:11:52 -07:00
Henry Cook
9ae6413273 periphery: peripherals now in coreplex (#26) 
* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster
 2017-07-23 08:31:44 -07:00
Megan Wachs
2bad829e6e gpio: Add missing file 2017-07-20 14:53:34 -07:00
Megan Wachs
06f0d20742 Add missing cloneType methods to pin bundles 2017-07-20 11:36:31 -07:00
Megan Wachs
00086c26e6 i2c: Remove pluralization on the bundle name, i2c not i2cs 2017-07-20 10:53:44 -07:00
Megan Wachs
ef4f2ed888 Remove pluralization on interface names. Require clocks and resets explicitly when necessary 2017-07-19 14:51:50 -07:00
Megan Wachs
4d74e8f67f Make it possible to adjust the type of pad controls used, 
and seperate out some of the "GPIO Peripheral" from "Pin Control"
 2017-07-19 08:01:42 -07:00
Henry Cook
fb9dd31374 Refactor package hierarchy. (#25) 2017-07-07 10:48:57 -07:00
Wesley W. Terpstra
66b2fd11bd vc707 axi enhancements (#24) 
1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
 2017-06-30 12:36:33 -07:00