riscv/sifive-blocks
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Merge pull request #6 from sifive/debug_v013

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Debug v013
This commit is contained in:
Megan Wachs 2017-03-31 15:14:35 -07:00 committed by GitHub
commit dbd16e305d
2 changed files with 13 additions and 13 deletions
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22
src/main/scala/devices/gpio/JTAG.scala
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@ -11,33 +11,31 @@ import Chisel._
// ------------------------------------------------------------ // ------------------------------------------------------------
import config._ import config._
import junctions.{JTAGIO} import jtag.{JTAGIO}
class JTAGPinsIO extends Bundle { class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {
val TCK = new GPIOPin() val TCK = new GPIOPin()
val TMS = new GPIOPin() val TMS = new GPIOPin()
val TDI = new GPIOPin() val TDI = new GPIOPin()
val TDO = new GPIOPin() val TDO = new GPIOPin()
val TRST_n = new GPIOPin() val TRSTn = if (hasTRSTn) Option(new GPIOPin()) else None
} }
class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module { class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module {
val io = new Bundle { val io = new Bundle {
val jtag = new JTAGIO(drvTdo) // TODO: make this not hard-coded true.
val pins = new JTAGPinsIO() val jtag = new JTAGIO(hasTRSTn)
val pins = new JTAGPinsIO(hasTRSTn)
} }
io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true)) io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true)) io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true)) io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))}
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
if (drvTdo) {
io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
}
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
io.pins.TDO.o.oe := io.jtag.TDO.driven
} }

4
src/main/scala/devices/spi/SPIArbiter.scala
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@ -20,7 +20,9 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits)) io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt)) io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt)) io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
io.outer.cs := Mux1H(sel, io.inner.map(_.cs)) // Workaround for overzealous combinational loop detection
io.outer.cs := Mux(sel(0), io.inner(0).cs, io.inner(1).cs)
require(n == 2, "SPIArbiter currently only supports 2 clients")
(io.inner zip sel).foreach { case (inner, s) => (io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s inner.tx.ready := io.outer.tx.ready && s