diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala
index 8734539..ba40bc6 100644
--- a/src/main/scala/devices/gpio/JTAG.scala
+++ b/src/main/scala/devices/gpio/JTAG.scala
@@ -11,33 +11,31 @@ import Chisel._
 // ------------------------------------------------------------
 
 import config._
-import junctions.{JTAGIO}
+import jtag.{JTAGIO}
 
-class JTAGPinsIO extends Bundle {
+class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {
 
   val TCK    = new GPIOPin()
   val TMS    = new GPIOPin()
   val TDI    = new GPIOPin()
   val TDO    = new GPIOPin()
-  val TRST_n = new GPIOPin()
+  val TRSTn  = if (hasTRSTn) Option(new GPIOPin()) else None
 
 }
 
-class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
+class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module {
 
   val io = new Bundle {
-    val jtag = new JTAGIO(drvTdo)
-    val pins = new JTAGPinsIO()
+    // TODO: make this not hard-coded true.
+    val jtag = new JTAGIO(hasTRSTn)
+    val pins = new JTAGPinsIO(hasTRSTn)
   }
 
   io.jtag.TCK  := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
   io.jtag.TMS  := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
   io.jtag.TDI  := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
-  io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
-
-  GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
-  if (drvTdo) {
-    io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
-  }
+  io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))}
 
+  GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
+  io.pins.TDO.o.oe := io.jtag.TDO.driven
 }
diff --git a/src/main/scala/devices/spi/SPIArbiter.scala b/src/main/scala/devices/spi/SPIArbiter.scala
index 56c484e..3c0c74a 100644
--- a/src/main/scala/devices/spi/SPIArbiter.scala
+++ b/src/main/scala/devices/spi/SPIArbiter.scala
@@ -20,7 +20,9 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
   io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
   io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
   io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
-  io.outer.cs := Mux1H(sel, io.inner.map(_.cs))
+  // Workaround for overzealous combinational loop detection
+  io.outer.cs := Mux(sel(0), io.inner(0).cs, io.inner(1).cs)
+  require(n == 2, "SPIArbiter currently only supports 2 clients")
 
   (io.inner zip sel).foreach { case (inner, s) =>
     inner.tx.ready := io.outer.tx.ready && s