From bf9b81f2bcaed9ed561906f66668dc98027671f8 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 2 Mar 2017 14:46:34 -0800 Subject: [PATCH 1/7] jtag: The jtag interfaces have moved to a different package. --- src/main/scala/devices/gpio/JTAG.scala | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala index 8734539..d16cf32 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/gpio/JTAG.scala @@ -11,7 +11,7 @@ import Chisel._ // ------------------------------------------------------------ import config._ -import junctions.{JTAGIO} +import jtag.{JTAGIO} class JTAGPinsIO extends Bundle { @@ -19,25 +19,22 @@ class JTAGPinsIO extends Bundle { val TMS = new GPIOPin() val TDI = new GPIOPin() val TDO = new GPIOPin() - val TRST_n = new GPIOPin() + val TRSTn = new GPIOPin() } -class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module { +class JTAGGPIOPort()(implicit p: Parameters) extends Module { val io = new Bundle { - val jtag = new JTAGIO(drvTdo) + val jtag = new JTAGIO() val pins = new JTAGPinsIO() } io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true)) io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true)) - io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true)) - - GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO) - if (drvTdo) { - io.pins.TDO.o.oe := io.jtag.DRV_TDO.get - } + io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true)) + GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data) + io.pins.TDO.o.oe := io.jtag.TDO.driven } From 77246eaada9532ff5f7dad1d4e293ac8b054236a Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 14 Mar 2017 14:52:39 -0700 Subject: [PATCH 2/7] Adjust JTAG for rocket-chip changes --- src/main/scala/devices/gpio/JTAG.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala index d16cf32..947955f 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/gpio/JTAG.scala @@ -19,21 +19,22 @@ class JTAGPinsIO extends Bundle { val TMS = new GPIOPin() val TDI = new GPIOPin() val TDO = new GPIOPin() - val TRSTn = new GPIOPin() + val TRSTn = new GPIOPin() } class JTAGGPIOPort()(implicit p: Parameters) extends Module { val io = new Bundle { - val jtag = new JTAGIO() + // TODO: make this not hard-coded true. + val jtag = new JTAGIO(hasTRSTn = true) val pins = new JTAGPinsIO() } io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true)) io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true)) - io.jtag.TRSTn := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true)) + io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true)) GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data) io.pins.TDO.o.oe := io.jtag.TDO.driven From c6d7326669d851e6d154a33822821f77703e1c3c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 21 Mar 2017 17:51:28 -0700 Subject: [PATCH 3/7] TLSPI: address parameter must now be a sequence. --- src/main/scala/devices/spi/TLSPI.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index b20b524..5c5b9bf 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -110,7 +110,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule { require(isPow2(c.rSize)) val device = new SimpleDevice("spi", Seq("sifive,spi0")) - val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w) + val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w) val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) } From faeb14dc5a6ade086a76a4d02806b3573a974f02 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 24 Mar 2017 17:27:55 -0700 Subject: [PATCH 4/7] JTAG: make TRSTn optional for all helpers as well to match the IO. --- src/main/scala/devices/gpio/JTAG.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/devices/gpio/JTAG.scala b/src/main/scala/devices/gpio/JTAG.scala index 947955f..ba40bc6 100644 --- a/src/main/scala/devices/gpio/JTAG.scala +++ b/src/main/scala/devices/gpio/JTAG.scala @@ -13,28 +13,28 @@ import Chisel._ import config._ import jtag.{JTAGIO} -class JTAGPinsIO extends Bundle { +class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle { val TCK = new GPIOPin() val TMS = new GPIOPin() val TDI = new GPIOPin() val TDO = new GPIOPin() - val TRSTn = new GPIOPin() + val TRSTn = if (hasTRSTn) Option(new GPIOPin()) else None } -class JTAGGPIOPort()(implicit p: Parameters) extends Module { +class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module { val io = new Bundle { // TODO: make this not hard-coded true. - val jtag = new JTAGIO(hasTRSTn = true) - val pins = new JTAGPinsIO() + val jtag = new JTAGIO(hasTRSTn) + val pins = new JTAGPinsIO(hasTRSTn) } io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true)) io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true)) - io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true)) + io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))} GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data) io.pins.TDO.o.oe := io.jtag.TDO.driven From 3c2277447dc4d7a60ad68eda7a50d81c280392e6 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 24 Mar 2017 21:38:31 -0700 Subject: [PATCH 5/7] rename l2FrontendBus as fsb --- .../devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index f37f7f9..d64d19a 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) - l2FrontendBus.node := xilinxvc707pcie.master + fsb.node := xilinxvc707pcie.master xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) intBus.intnode := xilinxvc707pcie.intnode From 6a3b5e1a31f0fa317d9ede581545ba27952ab1a4 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 30 Mar 2017 19:12:15 -0700 Subject: [PATCH 6/7] "Fix" false combinational loop through SPIArbiter Mux1H converts aggregates to UInt, muxes, then converts back which can look like a cominational loop. --- src/main/scala/devices/spi/SPIArbiter.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/SPIArbiter.scala b/src/main/scala/devices/spi/SPIArbiter.scala index 56c484e..df87d95 100644 --- a/src/main/scala/devices/spi/SPIArbiter.scala +++ b/src/main/scala/devices/spi/SPIArbiter.scala @@ -20,7 +20,9 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module { io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits)) io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt)) io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt)) - io.outer.cs := Mux1H(sel, io.inner.map(_.cs)) + // Workaround for overzealous combinational loop detection + io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs) + require(n == 2, "SPIArbiter currently only supports 2 clients") (io.inner zip sel).foreach { case (inner, s) => inner.tx.ready := io.outer.tx.ready && s From 70ac4044d1cfeb801ca4e16bc32da6339e82c1ab Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 31 Mar 2017 13:49:34 -0700 Subject: [PATCH 7/7] spi: correct polarity of FIRRTL combo loop detection workaround. --- src/main/scala/devices/spi/SPIArbiter.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/SPIArbiter.scala b/src/main/scala/devices/spi/SPIArbiter.scala index df87d95..3c0c74a 100644 --- a/src/main/scala/devices/spi/SPIArbiter.scala +++ b/src/main/scala/devices/spi/SPIArbiter.scala @@ -21,7 +21,7 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module { io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt)) io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt)) // Workaround for overzealous combinational loop detection - io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs) + io.outer.cs := Mux(sel(0), io.inner(0).cs, io.inner(1).cs) require(n == 2, "SPIArbiter currently only supports 2 clients") (io.inner zip sel).foreach { case (inner, s) =>