54 lines
1.6 KiB
Scala
54 lines
1.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.config.Field
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.none,
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arithmetic: Boolean = true,
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends TLBusParams {
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}
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case object PeripheryBusParams extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("PeripheryBus")
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def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
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TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
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}
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def toLargeBurstSlave(maxXferBytes: Int) = {
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TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
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}
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val fromSystemBus: TLInwardNode = {
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val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
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inwardBufNode := atomics.node
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atomics.node
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}
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasPeripheryBus extends HasSystemBus {
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private val pbusParams = p(PeripheryBusParams)
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val pbusBeatBytes = pbusParams.beatBytes
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val pbus = new PeripheryBus(pbusParams)
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// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus := sbus.toPeripheryBus
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}
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