15 lines
425 B
Scala
15 lines
425 B
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.tile.ResetVectorBits
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/** A single place for all tiles to find out the reset vector */
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trait HasResetVectorWire {
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implicit val p: Parameters
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val resetVectorBits = p(ResetVectorBits)
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val global_reset_vector = Wire(UInt(width = resetVectorBits))
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}
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