Stephen Twigg e90f2484aa Sync with riscv-opcodes (csr register mapping)

2014-04-08 15:48:37 -07:00

..

arbiter.scala

Fix D$ arbiter for >2 inputs

2014-03-04 16:32:17 -08:00

btb.scala

Bypass RAS push/pop

2014-04-07 23:47:53 -07:00

consts.scala

Move branch resolution to M stage

2014-04-07 15:58:49 -07:00

core.scala

New FP encoding; improved FP implementation

2014-03-11 18:58:24 -07:00

csr.scala

Make BTB more complexity-effective

2014-03-25 05:22:04 -07:00

ctrl.scala

Move branch resolution to M stage

2014-04-07 15:58:49 -07:00

decode.scala

Add return address stack

2014-04-01 15:01:27 -07:00

dpath_alu.scala

Move branch resolution to M stage

2014-04-07 15:58:49 -07:00

dpath.scala

Move branch resolution to M stage

2014-04-07 15:58:49 -07:00

ecc.scala

Make Int -> Bool conversions explicit

2014-03-24 04:36:53 -07:00

fpu.scala

Fix exception behavior of fmin/fmax

2014-03-18 18:36:51 -07:00

icache.scala

Move branch resolution to M stage

2014-04-07 15:58:49 -07:00

instructions.scala

Sync with riscv-opcodes (csr register mapping)

2014-04-08 15:48:37 -07:00

multiplier.scala

Add early out for MUL[W] (not MULH[[S]U])

2014-04-07 23:48:02 -07:00

nbdcache.scala

cleanups supporting uncore hierarchy

2014-01-31 12:07:26 -08:00

package.scala

Simplify handling of CAUSE register

2014-01-24 16:37:39 -08:00

ptw.scala

Clean up formatting (i.e. remove tabs, semicolons)

2014-01-13 21:43:56 -08:00

rocc.scala

hookup rocc interrupt and s bit

2014-02-06 00:09:42 -08:00

tile.scala

Make FPU pipeline depths configurable

2014-02-28 13:39:59 -08:00

tlb.scala

Clean up formatting (i.e. remove tabs, semicolons)

2014-01-13 21:43:56 -08:00

util.scala

Make BTB more complexity-effective

2014-03-25 05:22:04 -07:00