| .. |
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arbiter.scala
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Fix D$ arbiter for >2 inputs
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2014-03-04 16:32:17 -08:00 |
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btb.scala
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Bypass RAS push/pop
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2014-04-07 23:47:53 -07:00 |
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consts.scala
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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core.scala
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New FP encoding; improved FP implementation
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2014-03-11 18:58:24 -07:00 |
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csr.scala
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Make BTB more complexity-effective
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2014-03-25 05:22:04 -07:00 |
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ctrl.scala
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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decode.scala
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Add return address stack
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2014-04-01 15:01:27 -07:00 |
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dpath_alu.scala
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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dpath.scala
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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ecc.scala
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Make Int -> Bool conversions explicit
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2014-03-24 04:36:53 -07:00 |
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fpu.scala
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Fix exception behavior of fmin/fmax
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2014-03-18 18:36:51 -07:00 |
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icache.scala
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Move branch resolution to M stage
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2014-04-07 15:58:49 -07:00 |
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instructions.scala
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Sync with riscv-opcodes (csr register mapping)
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2014-04-08 15:48:37 -07:00 |
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multiplier.scala
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Add early out for MUL[W] (not MULH[[S]U])
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2014-04-07 23:48:02 -07:00 |
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nbdcache.scala
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cleanups supporting uncore hierarchy
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2014-01-31 12:07:26 -08:00 |
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package.scala
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Simplify handling of CAUSE register
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2014-01-24 16:37:39 -08:00 |
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ptw.scala
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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rocc.scala
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hookup rocc interrupt and s bit
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2014-02-06 00:09:42 -08:00 |
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tile.scala
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Make FPU pipeline depths configurable
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2014-02-28 13:39:59 -08:00 |
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tlb.scala
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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util.scala
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Make BTB more complexity-effective
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2014-03-25 05:22:04 -07:00 |
