| .. |
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ALU.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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Arbiter.scala
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Pipeline D$ exception response into s2
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2017-04-18 00:47:58 -07:00 |
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Breakpoint.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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BTB.scala
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Update RAS speculatively from fetch stage
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2017-04-24 02:01:15 -07:00 |
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Consts.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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CSR.scala
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Support vectored stvec interrupts, too
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2017-05-07 15:40:08 -07:00 |
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DCache.scala
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Support PutPartial in ScratchpadSlavePort
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2017-05-02 03:07:02 -07:00 |
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Decode.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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Events.scala
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Add performance counter facility
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2017-03-09 13:58:50 -08:00 |
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Frontend.scala
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tile: add tileBus xbar
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2017-05-16 16:12:01 -07:00 |
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HellaCache.scala
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tile: add tileBus xbar
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2017-05-16 16:12:01 -07:00 |
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IBuf.scala
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Don't stall the frontend, making it easier to add more features later
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2017-04-24 02:01:15 -07:00 |
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ICache.scala
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ITIM supports PutPartial
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2017-05-04 00:57:52 -07:00 |
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IDecode.scala
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Support PutPartial in ScratchpadSlavePort
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2017-05-02 03:07:02 -07:00 |
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Instructions.scala
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rocket: separate page faults from physical memory access exceptions
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2017-03-27 16:37:09 -07:00 |
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Multiplier.scala
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Support unrolling the integer divider
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2017-03-09 11:29:51 -08:00 |
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NBDcache.scala
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Support PutPartial in ScratchpadSlavePort
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2017-05-02 03:07:02 -07:00 |
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Package.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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PMP.scala
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Express PMP mask generation with incrementer, not adder
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2017-04-27 15:16:29 -07:00 |
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PTW.scala
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Check PPN LSBs for superpage PTEs
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2017-05-05 15:30:09 -07:00 |
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Rocket.scala
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Support PutPartial in ScratchpadSlavePort
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2017-05-02 03:07:02 -07:00 |
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RocketTiles.scala
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tile: add tileBus xbar
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2017-05-16 16:12:01 -07:00 |
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RVC.scala
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Heterogeneous Tiles (#550)
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2017-02-09 13:59:09 -08:00 |
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ScratchpadSlavePort.scala
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Merge branch 'master' into pipeline-mmio
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2017-05-02 16:23:26 -07:00 |
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SimpleHellaCacheIF.scala
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Support PutPartial in ScratchpadSlavePort
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2017-05-02 03:07:02 -07:00 |
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TLB.scala
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When not using a cache, LR/SC isn't legal even on cacheable memory
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2017-04-20 08:47:03 -07:00 |
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TLBPermissions.scala
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In TLBPermissions, merge across some region types
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2017-04-18 00:47:58 -07:00 |
