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Arbiters.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AsyncBundle.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AsyncQueue.scala
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Add 1-deep synchronizer register for output of AsyncQueue
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2017-08-28 17:18:54 -07:00 |
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AsyncResetReg.scala
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synchronizers: New chisel ways of cloning type and use simpler lambda function
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2017-08-30 12:11:14 -07:00 |
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Broadcaster.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ClockDivider.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Counters.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CRC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Crossing.scala
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util: delete old long-deprecated crossing code
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2017-10-26 13:58:52 -07:00 |
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ECC.scala
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rocket: base trait for reporting ecc errors
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2017-09-21 14:58:47 -07:00 |
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Frequency.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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GeneratorUtils.scala
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Bump Chisel and FIRRTL for annotations refactor (#1261)
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2018-03-07 10:22:38 -08:00 |
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GenericParameterizedBundle.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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HellaQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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HeterogeneousBag.scala
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Bump chisel and firrtl (#1232)
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2018-03-01 15:19:12 -08:00 |
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IdentityModule.scala
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util: add the IdentityModule, useful to dedup wires
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2017-09-07 16:03:35 -07:00 |
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LatencyPipe.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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LCG.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Misc.scala
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util: use chisel3.core.dontTouch
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2018-03-10 17:04:46 -08:00 |
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MultiWidthFifo.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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package.scala
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util: augment String and use to name couplers
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2018-02-21 14:43:47 -08:00 |
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PlusArg.scala
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Explicitly name PlusArg serializers as *_cHeader
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2018-01-15 17:00:12 -05:00 |
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PositionalMultiQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Property.scala
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Replace Parameters in cover with globally setable implementation (#1200)
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2018-01-18 14:45:36 -08:00 |
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PSDTestMode.scala
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test_mode_reset: use a cleaner interface with bundles and options instead of individual signals
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2017-09-15 12:30:39 -07:00 |
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RationalCrossing.scala
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RationalCrossing: use ShiftQueues
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2017-09-07 16:03:34 -07:00 |
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ReduceOthers.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ReorderQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Repeater.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Replacement.scala
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Make PseudoLRU policy support non-power-of-2 sizes
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2017-11-01 01:47:23 -07:00 |
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ResetCatchAndSync.scala
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ResetCatchAndSync: work also in the context of a RawModule (#1202)
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2018-01-19 19:45:52 -08:00 |
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ROMGenerator.scala
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tilelink: add mask rom
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2017-07-31 21:34:04 -07:00 |
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ShiftQueue.scala
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ShiftQueue: added a helper object
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2017-09-07 16:03:34 -07:00 |
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ShiftReg.scala
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Support SynchronizerShiftReg(sync = 0)
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2017-09-20 00:05:07 -07:00 |
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Timer.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
