riscv/rocket-chip
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52fc34a138
rocket-chip/rocket/src/main/scala
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Andrew Waterman 52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
2015-08-01 21:11:25 -07:00
..
arbiter.scala Use HeaderlessTileLinkIO 2015-04-13 15:58:10 -07:00
btb.scala Specify some uninferrable widths 2015-07-31 14:23:52 -07:00
consts.scala Chisel3 compatibility: use BitPat for don't-cares 2015-07-28 02:48:49 -07:00
csr.scala Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
decode.scala Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00
dpath_alu.scala Chisel3 compatibility: use BitPat for don't-cares 2015-07-28 02:48:49 -07:00
fpu.scala Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
icache.scala Chisel3: bulk connect is not commutative 2015-08-01 21:11:25 -07:00
idecode.scala Chisel3 compatibility: use BitPat for don't-cares 2015-07-28 02:48:49 -07:00
instructions.scala Chisel3 compatibility: use BitPat for don't-cares 2015-07-28 02:48:49 -07:00
multiplier.scala Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
nbdcache.scala Chisel3: bulk connect is not commutative 2015-08-01 21:11:25 -07:00
package.scala Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
ptw.scala Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
rocc.scala Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
rocket.scala Chisel3: bulk connect is not commutative 2015-08-01 21:11:25 -07:00
tile.scala Chisel3: bulk connect is not commutative 2015-08-01 21:11:25 -07:00
tlb.scala Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
util.scala Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00