Andrew Waterman 4807d7222b use replay to handle I$ misses ... this eliminates a long path in the fetch stage		2012-01-11 19:20:20 -08:00
..
arbiter.scala	require writes to memory to be uninterrupted	2012-01-03 18:41:53 -08:00
consts.scala	reduce superfluous replays	2012-01-01 21:28:38 -08:00
cpu.scala	remove icache req_rdy signal	2012-01-11 18:27:11 -08:00
ctrl_util.scala	remove second RF write port	2012-01-02 02:51:30 -08:00
ctrl.scala	use replay to handle I$ misses	2012-01-11 19:20:20 -08:00
dcache.scala	fix WAW hazard handling	2012-01-02 00:25:11 -08:00
divider.scala	move PCR writes to WB stage	2012-01-02 15:42:39 -08:00
dpath_alu.scala	reduce superfluous replays	2012-01-01 21:28:38 -08:00
dpath_util.scala	made tohost/fromhost 64 bits wide	2012-01-03 15:09:08 -08:00
dpath.scala	remove host.start signal, use reset instead	2012-01-11 17:49:32 -08:00
dtlb.scala	slight control logic cleanup	2012-01-11 16:56:40 -08:00
icache_prefetch.scala	hellacache returns!	2011-12-12 06:49:39 -08:00
icache.scala	use replay to handle I$ misses	2012-01-11 19:20:20 -08:00
instructions.scala	new mftx instruction format	2011-12-12 03:23:12 -08:00
itlb.scala	remove datapath register resets resets	2012-01-01 16:09:40 -08:00
multiplier.scala	move PCR writes to WB stage	2012-01-02 15:42:39 -08:00
nbdcache.scala	require writes to memory to be uninterrupted	2012-01-03 18:41:53 -08:00
ptw.scala	remove second RF write port	2012-01-02 02:51:30 -08:00
queues.scala	hellacache returns!	2011-12-12 06:49:39 -08:00
top.scala	use replay to handle I$ misses	2012-01-11 19:20:20 -08:00
util.scala	vlsi verilog compiles now but doesn't simulate	2011-12-20 22:08:27 -08:00