mwachs5 47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288)

2016-09-14 00:17:26 -07:00

..

Buffer.scala

tilelink2: add a clock crossing adapter

2016-09-13 18:33:56 -07:00

Bundles.scala

tilelink2 Bundles: fix wrong sink width!

2016-09-08 13:47:40 -07:00

Crossing.scala

tilelink2: add a clock crossing adapter

2016-09-13 18:33:56 -07:00

Edges.scala

tilelink2 HintHandler: fill in correct sink in responses

2016-09-12 17:26:40 -07:00

Example.scala

Merge remote-tracking branch 'origin/master' into black_box_regs

2016-09-09 13:12:52 -07:00

Fragmenter.scala

tilelink2: Fragmenter supports Hints

2016-09-12 17:31:59 -07:00

Fuzzer.scala

First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.

2016-09-13 20:30:14 -07:00

HintHandler.scala

tilelink2 HintHandler: don't HintAck in the middle of a multibeat op

2016-09-12 19:06:35 -07:00

IntNodes.scala

tilelink2 IntNodes: record interrupt ranges in parameters

2016-09-08 18:51:43 -07:00

LazyModule.scala

tilelink2: get rid of fragile implicit lazyModule pattern, and support :=

2016-09-08 23:06:59 -07:00

Legacy.scala

tilelink2 Legacy: it's only an error if it's valid (#264)

2016-09-08 21:09:40 -07:00

Monitor.scala

tilelink2: Hints are not special

2016-09-12 17:15:28 -07:00

Nodes.scala

tilelink2: get rid of fragile implicit lazyModule pattern, and support :=

2016-09-08 23:06:59 -07:00

package.scala

tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec

2016-09-08 21:34:20 -07:00

Parameters.scala

tilelink2 RAMModel: fix put, get, putAck, getAck case (#282)

2016-09-13 15:44:36 -07:00

RAMModel.scala

tilelink2 RAMModel: fix put, get, putAck, getAck case (#282)

2016-09-13 15:44:36 -07:00

RegField.scala

tilelink2: add a RegisterCrossing primitive

2016-09-13 18:33:53 -07:00

RegisterCrossing.scala

Give AsyncCrossing slave interfaces registers visibility into when they were written (#288)

2016-09-14 00:17:26 -07:00

RegisterRouter.scala

tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests

2016-09-12 10:32:24 -07:00

RegisterRouterTest.scala

tilelink2: Unit Test for the RegisterCrossing

2016-09-13 18:33:56 -07:00

RegMapper.scala

tilelink2: ensure RegFields don't exceed their bounds

2016-09-05 20:58:40 -07:00

SRAM.scala

TL2 WidthWidget (#258)

2016-09-08 10:38:38 -07:00

TLNodes.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00

WidthWidget.scala

tilelink2: get rid of fragile implicit lazyModule pattern, and support :=

2016-09-08 23:06:59 -07:00

Xbar.scala

tilelink2: refactor address into addr_hi on ABC and addr_lo on CD

2016-09-06 23:46:44 -07:00