117 lines
4.8 KiB
Scala
117 lines
4.8 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import uncore.util.{SimpleRegIO}
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case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
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object RegReadFn
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{
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// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
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// iready may combinationally depend on oready
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// iready must eventually go high without requiring ivalid to go high
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// ovalid must eventually go high without requiring oready to go high
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// effects must become visible on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
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new RegReadFn(false, x)
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implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
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RegReadFn((ivalid, oready) => {
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x.request.valid := ivalid
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x.response.ready := oready
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(x.request.ready, x.response.valid, x.response.bits)
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})
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// (ready: Bool) => (valid: Bool, data: UInt)
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// valid must not combinationally depend on ready
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// valid must eventually go high without requiring ready to go high
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// => this means that reading cannot trigger creation of the output data
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// if you need this, use the more general i&o ready-valid method above
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// effects must become visible on the cycle after valid && ready
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implicit def apply(x: Bool => (Bool, UInt)) =
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new RegReadFn(true, { case (_, oready) =>
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val (ovalid, data) = x(oready)
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(Bool(true), ovalid, data)
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})
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// read from a DecoupledIO (only safe if there is a consistent source of data)
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implicit def apply(x: DecoupledIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) })
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// read from a register
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implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (Bool(true), x))
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// noop
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implicit def apply(x: Unit):RegReadFn = RegReadFn(UInt(0))
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}
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case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
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object RegWriteFn
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{
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// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
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// iready may combinationally depend on both oready and data
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// iready must eventually go high without requiring ivalid to go high
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// ovalid must eventually go high without requiring oready to go high
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// effects must become visible on the cycle after ovalid && oready
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implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
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new RegWriteFn(false, x)
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implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
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RegWriteFn((ivalid, oready, data) => {
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x.request.valid := ivalid
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x.request.bits := data
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x.response.ready := oready
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(x.request.ready, x.response.valid)
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})
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// (valid: Bool, data: UInt) => (ready: Bool)
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// ready may combinationally depend on data (but not valid)
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// ready must eventually go high without requiring valid to go high
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// effects must become visible on the cycle after valid && ready
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implicit def apply(x: (Bool, UInt) => Bool) =
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// combinational => data valid on oready
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new RegWriteFn(true, { case (_, oready, data) =>
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(Bool(true), x(oready, data))
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})
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// write to a DecoupledIO (only safe if there is a consistent sink draining data)
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implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
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// updates a register (or adds a mux to a wire)
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implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) })
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// noop
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implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) })
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}
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case class RegField(width: Int, read: RegReadFn, write: RegWriteFn)
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{
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require (width > 0)
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def pipelined = !read.combinational || !write.combinational
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}
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object RegField
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{
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), ())
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def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw)
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def r(n: Int, r: RegReadFn) : RegField = apply(n, r, ())
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def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
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// This RegField allows 'set' to set bits in 'reg'.
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// and to clear bits when the bus writes bits of value 1.
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// Setting takes priority over clearing.
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def w1ToClear(n: Int, reg: UInt, set: UInt): RegField =
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RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }))
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// This RegField wraps an explicit register
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// (e.g. Black-Boxed Register) to create a R/W register.
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def rwReg(n: Int, bb: SimpleRegIO) : RegField =
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RegField(n, bb.q, RegWriteFn((valid, data) => {
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bb.en := valid
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bb.d := data
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Bool(true)
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}))
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}
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trait HasRegMap
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{
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def regmap(mapping: RegField.Map*): Unit
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val interrupts: Vec[Bool]
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}
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// See GPIO.scala for an example of how to use regmap
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