| .. |
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arbiter.scala
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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consts.scala
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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cpu.scala
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added ld/st misaligned exceptions
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2011-11-13 00:03:17 -08:00 |
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ctrl_util.scala
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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ctrl.scala
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added timer interrupt support
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2011-11-13 00:27:57 -08:00 |
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dcache.scala
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added ld/st misaligned exceptions
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2011-11-13 00:03:17 -08:00 |
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divider.scala
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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dpath_alu.scala
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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dpath_util.scala
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added timer interrupt support
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2011-11-13 00:27:57 -08:00 |
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dpath.scala
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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dtlb.scala
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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icache_prefetch.scala
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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icache.scala
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cache optimizations, cleanup, and testharness improvement
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2011-11-12 22:13:29 -08:00 |
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instructions.scala
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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itlb.scala
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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multiplier.scala
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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ptw.scala
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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queues.scala
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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top.scala
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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util.scala
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
