Wesley W. Terpstra 147fad6387 Fix AXI4 FIFO ordering for masters with early source reuse (#1108) ... * TLToAXI4: fix WaR for single-source FIFO masters * TLToAXI4: fix potential counter overflow => WaR hazard If you have a FIFO master with 2^n-1 sources that performs early source re-use, the old code could potentially break FIFO order.		2017-11-13 20:32:09 -08:00
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scala	Fix AXI4 FIFO ordering for masters with early source reuse (#1108)	2017-11-13 20:32:09 -08:00