Henry Cook
3030718f72
bump chisel3
2016-09-14 17:40:22 -07:00
Henry Cook
08c4c7b985
[junctions] make async crossings capable of providing IrrevocableIO
2016-09-14 17:38:54 -07:00
mwachs5
ae026edeb3
Merge pull request #293 from ucb-bar/async_clk_utils
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Add some async/clock utilities
2016-09-14 16:59:27 -07:00
Megan Wachs
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020
Move BootROM from Coreplex to Periphery
2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3
[tilelink2] Monitor: miscopied name in assert message
2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab
[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
2016-09-14 14:23:23 -07:00
Scott Beamer
f7121a2a5b
support for BSD sed (GNU sed still works)
2016-09-14 12:21:39 -07:00
Scott Beamer
cd12fd1cbb
fix clang support for emulator-debug
2016-09-14 12:20:37 -07:00
Andrew Waterman
565444c40e
Make UnitTestCoreplex cope with an external MMIO network
2016-09-14 12:19:21 -07:00
Andrew Waterman
2572cd3f7c
Add missing dependency
2016-09-14 11:50:28 -07:00
Andrew Waterman
5828e6042e
Work around https://github.com/ucb-bar/firrtl/issues/299
2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b
Move PRCI from Coreplex to always-on block, where it belongs
2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13
Don't route PLIC interrupts through PRCI
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The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
Andrew Waterman
38b13da2f4
Bump chisel and firrtl
2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b
Give AsyncCrossing slave interfaces registers visibility into when they were written ( #288 )
2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36
move tilelink-agnostic counters from uncore to util package
2016-09-13 20:47:05 -07:00
Howard Mao
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
dfd6bfb454
Merge pull request #287 from ucb-bar/crossing-take-2
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Clock crossing redux
2016-09-13 19:13:21 -07:00
Wesley W. Terpstra
d23ab7370d
tilelink2: Unit Test for the RegisterCrossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08
junctions: give unit tests more time
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a
tilelink2: unit test for the clock crossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884
tilelink2: add a clock crossing adapter
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8
crossings: change defaults to sync=3 for safer settling time
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Make the matching AsyncQueue depth=8 to support full throughput
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320
junctions: remove obsolete Handshaker crossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e
tilelink2: add a RegisterCrossing primitive
2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34
junctions: add an AsyncQueue
2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e
junctions: refactor the Crossing type
2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5
crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain
2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db
tilelink2 RAMModel: fix put, get, putAck, getAck case ( #282 )
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This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
2016-09-13 15:44:36 -07:00
Henry Cook
28982ab569
Merge pull request #279 from ucb-bar/monitor
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TL2 Monitor and Fuzzer
2016-09-13 14:04:23 -07:00
Henry Cook
632b5896b9
Delete TestGraphs.scala
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Re-do later using Fuzzer
2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48
[tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments.
2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7
Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor
2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d
Add option to execute JAL from decode stage
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This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC. Caveat emptor.
2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f
tilelink2: RegisterRouter Unit Test
2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651
tilelink2 HintHandler: don't HintAck in the middle of a multibeat op
2016-09-12 19:06:35 -07:00
roman3017
2979badf75
Update README.md
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Fixed path to Configs.scala
2016-09-12 18:55:14 -07:00
Wesley W. Terpstra
273d3a73f2
tilelink2: Unit Test passes!
2016-09-12 18:39:50 -07:00
Colin Schmidt
a10d058e1a
fix warnings in verilog source ( #274 )
2016-09-12 18:25:35 -07:00
Wesley W. Terpstra
9874bc553a
tilelink2: Fragmenter supports Hints
2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490
tilelink2: HintHandler optimize to nothing if unneeded
2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d
tilelink2 HintHandler: fill in correct sink in responses
2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138
tilelink2: Hints are not special
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Hints have a TransferSize limit just like all other message types.
2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89
[tilelink2] Fuzzer: Rewrite of fuzzer
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Multiple bug-fixes and actual source id generation.
2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179
[tilelink2] Monitor: Allow zero-mask PutPartials
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this will require a larger address refactoring TBD
2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86
tilelink2 Fragmenter: bugfix using D.hasData
2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb
[tilelink2] Edges: add size to addr_lo.
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addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89
Use PseudoLRU in BTB when possible (for powers of two)
2016-09-12 16:52:03 -07:00
