Andrew Waterman
f57524e0c1
Remove FENCE.I from debug ROM; specialize for RV64
2016-06-23 00:01:26 -07:00
mwachs5
2d2096e509
Add smaller ROM/RAM for 32-bit debug ( #60 )
2016-06-15 15:07:43 -07:00
Megan Wachs
cee0cf345e
[debug] Update Debug ROM contents to write F..F to RAM in case of exception
2016-06-09 14:05:30 -07:00
mwachs5
93c1b17b52
[debug] Remove erroneous buffer on SB read data ( #56 )
2016-06-08 23:31:13 -04:00
Megan Wachs
b832689642
Correct Debug ROM contents
2016-06-05 19:35:25 -07:00
Megan Wachs
605fb5b92f
[debug]: fix issue with subword select logic
2016-06-05 19:31:07 -07:00
Megan Wachs
3e8322816b
Correct DMINFO Fields
2016-06-05 19:29:50 -07:00
Megan Wachs
7e550ab07c
[debug] rocket: fix for issue 121, correct debug ROM and stall logic
2016-06-05 19:29:44 -07:00
Andrew Waterman
0866b4c045
Can't assign to Vec literals
2016-06-01 23:36:34 -07:00
Andrew Waterman
20e1de08da
Avoid chisel2 pitfall
...
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3. D'oh.
2016-06-01 23:35:49 -07:00
Andrew Waterman
5629fb62bf
Avoid bitwise sub-assignment
2016-06-01 21:59:02 -07:00
Andrew Waterman
9518b3d589
Fix arithmetic in ROM row count
2016-06-01 21:59:02 -07:00
Andrew Waterman
8e80d1ec80
Avoid floating-point arithmetic where integers suffice
2016-06-01 21:59:02 -07:00
mwachs5
740a6073f6
Add Debug Module ( #49 )
...
* Add Debug Module
* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents
* [debug] Update Debug ROM contents to match updated addresses
2016-06-01 16:33:33 -07:00
