riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. TerpstraandAndrew Waterman ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. TerpstraandAndrew Waterman 3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. TerpstraandAndrew Waterman d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. TerpstraandAndrew Waterman 2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. TerpstraandAndrew Waterman 2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. TerpstraandAndrew Waterman 31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. TerpstraandAndrew Waterman 7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. TerpstraandAndrew Waterman f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Wesley W. TerpstraandAndrew Waterman 976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Wesley W. TerpstraandAndrew Waterman da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00