Wesley W. Terpstra
93b2fa197e
Artefact output ( #545 )
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* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
Colin Schmidt
f19d504c88
Use % in makefrag-verilog to prevent double firrtl execution ( #452 )
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* Use % in makefrag-verilog to prevent double firrtl execution
2016-11-25 01:50:01 -08:00
Andrew Waterman
f3c726033a
Make all Chisel invocations depend on FIRRTL_JAR
2016-10-28 11:56:05 -07:00
Jack Koenig
288d7169ae
Bump firrtl and update vsim Makefrag-verilog ( #409 )
2016-10-23 23:07:47 -07:00
Henry Cook
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
Henry Cook
2961d92244
[testharness] vsim makefrag cleanup
2016-09-19 15:14:45 -07:00
Henry Cook
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
Howard Mao
8550582f84
remove redundant verilator rule
2016-09-14 20:31:17 -07:00
jackkoenig
a304695ffd
Add firrtl and verilog Makefile targets to vsim
2016-09-14 20:29:59 -07:00
Ben Keller
6be569be9f
Turn on the inferRW Firrtl pass
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Without this, all of the memories wind up as two-ported.
2016-09-07 15:27:26 -07:00
Megan Wachs
e95fe646a3
mem_gen failure doesn't create the target
2016-09-06 16:29:29 -07:00
Megan Wachs
48098f5e2d
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 14:48:28 -07:00
Howard Mao
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
Henry Cook
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
Andrew Waterman
ed827678ac
Write test harness in Chisel
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This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
Howard Mao
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
Howard Mao
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
Howard Mao
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
Palmer Dabbelt
e6c4372332
Fix "make run-asm-tests" for Chisel 3
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This was just a missing Makefrag-verilog dependency (the .d file).
2016-06-06 21:36:55 -07:00
Wesley W. Terpstra
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
Howard Mao
18ffe7b1ec
don't use +verbose in vsim .run rule
2016-05-04 23:01:14 -07:00
Andrew Waterman
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Howard Mao
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
Howard Mao
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
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This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
Palmer Dabbelt
cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Christopher Celio
83df4bcc35
Fixed run-bmark-tests make target in vsim
2015-09-09 22:37:47 -07:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
