Andrew Waterman
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1e1926ce63
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flip direction of ioPipe to match ioDecoupled
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2012-03-02 16:18:32 -08:00 |
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Yunsup Lee
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8678b3d70c
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clean up ioDecoupled/ioPipe interface
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2012-03-01 20:48:46 -08:00 |
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Andrew Waterman
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52101373e0
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clean up D$ store data unit
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2012-03-01 19:20:00 -08:00 |
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Andrew Waterman
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b9ec69f8f5
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add new Queue singleton
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2012-02-29 14:21:42 -08:00 |
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Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Andrew Waterman
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4121fb178c
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clean up mul/div interface; use VU mul if HAVE_VEC
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2012-02-24 19:22:35 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Andrew Waterman
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a1855b12c2
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clean up queues
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2012-02-08 17:55:05 -08:00 |
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Henry Cook
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8766438bb9
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Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
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Andrew Waterman
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31c56228e2
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add missing "otherwise"
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2012-01-21 20:13:15 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Andrew Waterman
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8f3927fdfa
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queue data type is now templated
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2011-11-30 18:08:26 -08:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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