 Stephen Twigg
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8c96e27ca6
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Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
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2014-02-04 17:20:28 -08:00 |
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Stephen Twigg
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8062888fb9
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Push hwacha, rocket, chisel to newest versions
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2014-01-28 22:15:41 -08:00 |
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Stephen Twigg
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e7ee94bcc8
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Merge branch 'master' into hwacha-port
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2014-01-21 15:23:05 -08:00 |
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Stephen Twigg
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ee0c4ca291
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Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
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2014-01-21 14:48:04 -08:00 |
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Stephen Twigg
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3eafbbd1e2
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Push hwacha, rocket. All physical tests pass.
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2013-11-19 22:16:27 -08:00 |
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Stephen Twigg
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d7c6824c51
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Push riscv-tests and riscv-tools
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2013-11-18 13:30:02 -08:00 |
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Stephen Twigg
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e50c5180cd
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Merge branch 'master' into hwacha
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2013-11-14 16:03:55 -08:00 |
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Stephen Twigg
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36e715a797
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Use newer version of hwacha (still not quite working but no longer stalls)
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2013-11-14 15:56:51 -08:00 |
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Stephen Twigg
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a870f51300
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Add some vector tests
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2013-11-14 15:56:25 -08:00 |
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Stephen Twigg
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3cdfde9861
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Push hwacha, rocket
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2013-11-05 15:31:59 -08:00 |
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Stephen Twigg
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7da65434ee
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Initial commit for the hwacha reference-chip/rocket re-integration.
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2013-10-30 20:44:02 -07:00 |
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Stephen Twigg
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437f7ed4af
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Push hardfloat (ignore target files)
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2013-09-26 20:51:19 -07:00 |
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Stephen Twigg
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f6d7e22c46
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Push rocket (fix issue with uppermost bit of D$ req tag getting lost)
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2013-09-25 11:52:01 -07:00 |
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Stephen Twigg
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36dfff5ee8
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Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.
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2013-09-25 01:21:41 -07:00 |
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Stephen Twigg
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eb7e6f03b3
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push rocket (AccumulatorExample fixes and documentation)
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2013-09-24 16:33:32 -07:00 |
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Stephen Twigg
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472b947fbe
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push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory)
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2013-09-24 16:16:12 -07:00 |
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Stephen Twigg
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eb03f61058
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Properly ignore target files. Push uncore (properly ignore target files)
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2013-09-24 16:03:28 -07:00 |
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Stephen Twigg
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081fcc4e63
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push rocket (accelerator interface fixes)
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2013-09-24 10:55:22 -07:00 |
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Stephen Twigg
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fba0ae0fec
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Push rocket
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2013-09-23 00:26:27 -07:00 |
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Stephen Twigg
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324a6321bd
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Push tools (improve consistency: these tools will compile/test the new ISA encoding)
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2013-09-22 03:24:11 -07:00 |
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Stephen Twigg
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2676ea8279
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Push rocket (fix some issues with RoCC although some remain)
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2013-09-22 03:19:43 -07:00 |
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Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Stephen Twigg
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f27c0fb010
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Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
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2013-09-05 15:01:56 -07:00 |
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Stephen Twigg
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
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Stephen Twigg
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c1b1a21a0f
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If +stats is set when running simv-debug, will only output vcd data when cr28 is high.
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2013-07-30 16:39:47 -07:00 |
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Stephen Twigg
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3f874342a4
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Update chisel to appropriate version for reference chip build.
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2013-07-10 17:08:56 -07:00 |
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Stephen Twigg
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bd43ca8423
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-05-23 17:51:24 -07:00 |
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