50c85f1b62
TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 15:46:06 -07:00
ba4eecc0f0
Use UIntToOH1 ( #921 )
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Closes #920
2017-08-03 14:55:39 -07:00
f483bab4aa
Fix I$ miss perfctr
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The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
1be1433f04
Merge pull request #918 from freechipsproject/icache-prefetch
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Icache prefetch
2017-08-02 21:22:20 -07:00
d66e8f8e80
Merge pull request #914 from freechipsproject/critical-paths
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Fix some critical paths
2017-08-02 19:05:31 -07:00
3fc7100048
Merge pull request #917 from freechipsproject/fuzzer_order
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TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 18:39:59 -07:00
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
744cdb2f72
Make TLB report when it's safe to prefetch within a page
2017-08-02 17:09:38 -07:00
d9821a74ce
Merge pull request #916 from freechipsproject/transfer_sizes_print
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diplomacy: Pretty Print for TransferSizes
2017-08-02 16:56:36 -07:00
595415d207
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
fc5c04ed4b
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 14:44:18 -07:00
7d2dd3769f
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
85bdae0fa8
diplomacy: Pretty Print for TransferSizes
2017-08-02 11:40:50 -07:00
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
9464c6db40
Mitigate(?) frontend critical path
2017-08-01 18:51:17 -07:00
735701382f
Mitigate some I$ response valid critical paths
2017-08-01 18:51:17 -07:00
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
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This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
f988b91575
Merge pull request #912 from freechipsproject/add-mask-rom
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tilelink: add mask rom
2017-07-31 22:28:11 -07:00
6ef8ee5d4d
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
4b33249812
Merge pull request #911 from freechipsproject/fix-dcache-bug
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Fix D$ ready-valid signaling bug
2017-07-31 19:14:16 -07:00
42ff74bd34
Merge pull request #910 from freechipsproject/tilelink-map
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Tilelink map
2017-07-31 18:33:09 -07:00
e140893a01
Use 1-entry queue on processor-side E-channel
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The cache can't sink a grant every cycle, so extra E buffering doesn't help.
2017-07-31 18:06:54 -07:00
5681693ccc
Fix a D$ ready-valid signaling regression
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I broke this in 66d06460fa
2017-07-31 18:05:14 -07:00
d7fd9d2b82
tilelink: Filter, add another case
2017-07-31 16:51:26 -07:00
71a250b071
Merge pull request #909 from freechipsproject/tile-buffer
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add optional tile boundary buffers
2017-07-31 16:46:22 -07:00
b126105230
tilelink: add TLMap to make it possible to move slaves
2017-07-31 16:39:00 -07:00
13d3ffbcaa
tilelink: Filter now support arbitrary filter functions
2017-07-31 16:38:38 -07:00
7adfd5c431
Merge pull request #906 from freechipsproject/critical-paths
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Mitigate I$->D$->I$ critical path
2017-07-31 16:14:11 -07:00
07b4edfc87
Merge pull request #908 from freechipsproject/combo-breaker
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dcache: break potential combinatorial loop
2017-07-31 16:13:01 -07:00
f473e6bad0
tile: add optional boundary buffers
2017-07-31 15:57:22 -07:00
cb3529bbc3
util: tweak rational crossings to avoid mux in source
2017-07-31 15:10:15 -07:00
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
d811692c3b
Mitigate I$->D$->I$ critical path
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This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
2017-07-31 01:43:04 -07:00
ea1840c4b1
Merge pull request #904 from freechipsproject/fix-dcache-bug
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Fix D$ ready-valid signaling bug
2017-07-29 20:30:47 -07:00
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
8e2e931770
Merge pull request #903 from freechipsproject/monitor-probes
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tilelink: use the Monitor to enforce Probe sourcing
2017-07-29 01:12:08 -07:00
56e28026a6
TLError: does not need to be fast; cut the loop
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The SystemBus already has a flow buffer on outputs.
2017-07-29 00:22:21 -07:00
540256e24a
systembus: all slaves should have an output buffer
2017-07-29 00:13:33 -07:00
eadf4e9fcc
Revert "tile: add option for tile boundary buffers"
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This reverts commit b64b87ad07
2017-07-29 00:03:24 -07:00
68064ba260
systembus: don't double down on buffers
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The order should be:
master => buffer|xing => fifofixer => splitter => xbar
2017-07-29 00:02:12 -07:00
140086e2c5
Merge pull request #902 from freechipsproject/perf-improvements
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Perf improvements
2017-07-28 20:12:10 -07:00
a0db929003
tilelink: use the Monitor to enforce Probe sourcing
2017-07-28 18:08:00 -07:00
573890e102
Merge pull request #900 from freechipsproject/more_verbose_requires
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diplomacy: More verbose require
2017-07-28 13:23:33 -07:00
fdb8935712
Improve fidelity of two perf counters
2017-07-28 13:14:04 -07:00
4c82f6b77e
Don't refill BTB on not-taken branches
2017-07-28 13:13:52 -07:00
2e8b02e780
Merge D$ store hits when ECC is enabled
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This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
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The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
ae1f7a95f6
Don't nack misses when there's a pending store
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That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
7eeb9dfd88
Merge pull request #899 from freechipsproject/wrapper-dedup
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Stabilize tile wrappers for downstream tools
2017-07-28 10:52:59 -07:00
Megan Wachs
Andrew Waterman
Andrew Waterman
Yunsup Lee
Wesley W. Terpstra
Henry Cook