Andrew Waterman
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
Wesley W. Terpstra
31a934bec0
coreplex: buses are now LazyModules with LazyScope
2017-09-26 14:58:56 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Henry Cook
b86f4b9bb7
config: use Field defaults over Config defaults
...
Also rename some keys that had the same class name as their value's class name.
2017-09-13 11:25:42 -07:00
Henry Cook
9c0bfbd500
tile: remove global Field ResetVectorBits
...
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
2017-09-08 14:50:59 -07:00
Wesley W. Terpstra
b1cacc56ad
SystemBus: restore correct order of FIFOFixer and Buffer
2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
e65f49b89a
FrontBus: attach to splitter for cross-chip visibility
2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a
sbus => pbus: 2 buffers should already be enough
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There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.
Between them is only an AtomicAutomata.
That should be enough for most designs.
2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987
pbus: clarify that we are adding buffers when attaching to sbus
2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
Megan Wachs
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
...
This should probably be reverted.
2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
656609d610
SystemBus: split FIFOFixers along bus boundaries
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If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
Wesley W. Terpstra
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
Megan Wachs
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
Wesley W. Terpstra
17134125e1
SystemBus: remove misnamed functions ( #972 )
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These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
Henry Cook
2910d6fa2a
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
Wesley W. Terpstra
540256e24a
systembus: all slaves should have an output buffer
2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
68064ba260
systembus: don't double down on buffers
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The order should be:
master => buffer|xing => fifofixer => splitter => xbar
2017-07-29 00:02:12 -07:00
Wesley W. Terpstra
2e4f1611ed
tilelink: Error device supports Acquire
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We need this if we want to divert traffic to it from a TL-C slave.
2017-07-27 18:32:58 -07:00
Wesley W. Terpstra
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
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* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
