130 lines
4.8 KiB
Scala
130 lines
4.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class SystemBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.default
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) extends TLBusParams
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case object SystemBusKey extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
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private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
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master_splitter.suggestName(s"${busName}_master_TLSplitter")
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inwardNode :=* master_splitter.node
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def busView = master_splitter.node.edges.in.head
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protected def inwardSplitNode: TLInwardNode = master_splitter.node
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protected def outwardSplitNode: TLOutwardNode = master_splitter.node
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private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
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master_splitter.node :=* tile_fixer.node
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private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
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master_splitter.node :=* port_fixer.node
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private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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pbus_fixer.suggestName(s"${busName}_pbus_TLFIFOFixer")
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pbus_fixer.node :*= outwardWWNode
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def toSplitSlaves: TLOutwardNode = outwardSplitNode
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def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
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val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
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in := pbus_fixer.node
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out
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}
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val toMemoryBus: TLOutwardNode = outwardNode
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val toSlave: TLOutwardNode = outwardBufNode
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def fromCoherentChip: TLInwardNode = inwardNode
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def fromFrontBus: TLInwardNode = master_splitter.node
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def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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val tile_buf = LazyModule(new TLBuffer(params))
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name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }
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val (in, out) = bufferChain(addBuffers, name = name)
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tile_fixer.node :=* out
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in :=* tile_buf.node
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tile_buf.node
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}
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def fromRationalTiles(dir: RationalDirection, addBuffers: Int = 0, name: Option[String] = None): TLRationalInwardNode = {
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val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
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name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
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val (in, out) = bufferChain(addBuffers, name = name)
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tile_fixer.node :=* out
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in :=* tile_sink.node
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tile_sink.node
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}
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def fromAsyncTiles(depth: Int, sync: Int, addBuffers: Int = 0, name: Option[String] = None): TLAsyncInwardNode = {
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val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
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val (in, out) = bufferChain(addBuffers, name = name)
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tile_fixer.node :=* out
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in :=* tile_sink.node
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tile_sink.node
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}
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def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
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val buffer = LazyModule(new TLBuffer(params))
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name.foreach { n => buffer.suggestName(s"${busName}_${n}_TLBuffer") }
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port_fixer.node :=* buffer.node
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buffer.node
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}
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def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
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fromSyncPorts(params, name)
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}
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def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
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port_fixer.node :=* sink.node
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sink.node
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}
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def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
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def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
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val sink = LazyModule(new TLRationalCrossingSink(dir))
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name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
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port_fixer.node :=* sink.node
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sink.node
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}
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def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasSystemBus extends HasInterruptBus {
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private val sbusParams = p(SystemBusKey)
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val sbusBeatBytes = sbusParams.beatBytes
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val sbus = LazyModule(new SystemBus(sbusParams))
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def sharedMemoryTLEdge: TLEdge = sbus.busView
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def paddrBits: Int = sbus.busView.bundle.addressBits
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}
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