Yunsup Lee
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8678b3d70c
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clean up ioDecoupled/ioPipe interface
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2012-03-01 20:48:46 -08:00 |
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Yunsup Lee
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bfd0ae125e
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upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
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2012-02-26 23:46:51 -08:00 |
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Andrew Waterman
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2d04664a98
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simplify cpu-cache interface
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2012-02-26 18:26:29 -08:00 |
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Yunsup Lee
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f3bb02b2ea
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refactored dmem arbiter
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2012-02-26 17:38:08 -08:00 |
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Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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3045b33460
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remove second RF write port
load miss writebacks are treated like mul/div now.
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2012-01-02 02:51:30 -08:00 |
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Andrew Waterman
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2f8fcebea0
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remove datapath register resets resets
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2012-01-01 16:09:40 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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ce201559f3
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Support cache->cpu nacks one cycle after request
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2011-12-10 00:42:09 -08:00 |
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Rimas Avizienis
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83d90c4dab
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
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Rimas Avizienis
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a1ce908541
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dcache/dtlb overhaul
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2011-11-11 18:18:47 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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