riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,550 Commits 1 Branch 0 Tags 13 MiB
d13dc8ac2a
Commit Graph

2294 Commits

Author SHA1 Message Date
Wesley W. Terpstra
0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Wesley W. Terpstra
c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
a4ca424a22 AHBToTL: finally get the error signal right? (#594) 2017-03-18 22:24:20 -07:00
Wesley W. Terpstra
f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) 2017-03-17 19:34:40 -07:00
Megan Wachs
dcc9827ab4 Rename Prci.scala to Clint.scala (#591) 
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
 2017-03-17 15:36:10 -07:00
Wesley W. Terpstra
db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
9b5b3279a6 AHBToTL: don't report error during idle cycles 2017-03-16 18:18:29 -07:00
Wesley W. Terpstra
5efd38bf97 apb: put both aFlow options under regression 2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33 axi4: use common BufferParams 2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094 unittest: try both aFlow settings of TLToAHB 2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
c95c2ca9c8 AHB: include bridge unit tests 2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089 ahb: implement a ToTL bridge 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925 apb: better test coverage 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5 axi4: improve test harness 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1 tilelink2: optimize the supportsX check circuits 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409 tilelink2: make TLBuffer API more flexible 2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing 
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
 2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c Merge branch 'master' into priv-1.10 2017-03-13 21:40:12 -07:00
Leway Colin
1322a02637 Fixed Hasti can't handle N masters to one slave #571 (#576) 2017-03-13 20:36:53 -07:00
Andrew Waterman
d6f571cbbb Implement mstatus.TSR 2017-03-13 14:50:06 -07:00
Andrew Waterman
1fea0460ba Support superpage entries in TLB 2017-03-13 14:50:06 -07:00
Andrew Waterman
2d267b4940 Support corner cases in TLBPermissions 
Don't crap out if the yes-set or no-set is empty.
 2017-03-13 14:50:06 -07:00
Andrew Waterman
90b5cc96cb Gracefully handle empty ports in AddressDecoder 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
c847559853 TLB: add a helper API to determine homogeneous page permissions 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
eaf474a081 LFSR: use random intial value of the start register 
We just need to make sure it doesn't initialize randomly stuck at 0.
 2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0 Merge branch 'master' into priv-1.10 2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd Zap conflicting TLB entries, preparing for superpage support 
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation.  This
isn't compatible with the Mux1H approach.  So, flush the TLB and report
a miss on duplicate entries.
 2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb Don't double-count release traffic in perfctrs 2017-03-09 16:49:02 -08:00
Andrew Waterman
63f8ce36f6 Avoid VM exceptions in groundtest by setting Accessed bit 2017-03-09 16:48:28 -08:00
Andrew Waterman
4f8f05d635 Add performance counter facility 2017-03-09 13:58:50 -08:00
Andrew Waterman
33b6d48376 Fix haltnot reporting (previously always returned 0) 2017-03-09 13:58:40 -08:00
Andrew Waterman
24a2278fc4 Perform all illegal-instruction detection in ID stage 
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
 2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741 Support unrolling the integer divider 2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf Improve BTB critical path at slight accuracy cost 
Make entries fully associative on lower 14 bits only, not full address.
 2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines 
It's redundant with the new scheme, so just adds HW for no reason.
 2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac Use sNaN value for flw, like other single-precision ops 2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result 
We were zero-extending it, which is a double-precision zero in the recoded
format.  So, when spilled and reloaded with fsd/fld, the original value
was destroyed.  Instead, set the MSBs so that it represents sNaN.  When
spilled, the single-precision number will be preserved as the NaN payload.
 2017-03-07 20:51:32 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry Cook
229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Wesley W. Terpstra
676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra
1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra
0178248551 diplomacy: evaluate ResourceBindings only once 2017-03-03 02:04:17 -08:00
Wesley W. Terpstra
8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra
7660be039c rocketchip: add WithTimebase to set RTC frequency 2017-03-03 00:47:50 -08:00
Wesley W. Terpstra
57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
Wesley W. Terpstra
4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra
e322692d16 diplomacy: add DeviceTree renderer 2017-03-02 21:19:14 -08:00
Wesley W. Terpstra
c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet 2017-03-02 11:14:28 -08:00
Wesley W. Terpstra
bb70b1a3c3 diplomacy: add resource tracking 2017-03-02 11:14:28 -08:00
Henry Cook
9bfcb40cb4 util: Majority on sets of bools 2017-02-27 20:18:28 -08:00
Henry Cook
6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments 2017-02-27 19:40:55 -08:00
Henry Cook
62f5727bc6 periphery: peripheryBusBytes and socBusBytes 2017-02-27 19:19:41 -08:00
Andrew Waterman
dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold 
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
  use of holdUnless
 2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Henry Cook
35877e6ec1 Merge branch 'master' into periphery-adjustments 2017-02-24 10:37:41 -08:00
Leway Colin
87d909e996 Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) 2017-02-24 10:37:26 -08:00
Henry Cook
a281ad8ad2 rocketchip: rename some periphery ports 2017-02-23 18:28:04 -08:00
Henry Cook
6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] 2017-02-23 18:27:44 -08:00
Wesley W. Terpstra
c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Henry Cook
027d6247b6 diplomacy: silence a warning (#560) 2017-02-22 11:28:04 -08:00
Wesley W. Terpstra
9153a9a733 ClockDivider: add docs to appease the reviewer 
... even though this means a delay of 1:30 hours :(
 2017-02-17 19:35:08 +01:00
Wesley W. Terpstra
3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Wesley W. Terpstra
5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) 
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
 2017-02-17 14:26:23 +01:00
Wesley W. Terpstra
924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra
bb334a2cf5 util: add fast2slow direction option to rational crossings 
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
 2017-02-17 13:59:51 +01:00
Wesley W. Terpstra
e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. Terpstra
abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Jacob Chang
5fc44bbcda Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554) 2017-02-10 10:19:22 -08:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Jim Lawson
307e0ca9c0 Fix up Absolute value. 
As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt.
 2017-02-08 15:00:43 -08:00
Wesley W. Terpstra
69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) 2017-02-04 15:59:50 -08:00
Wesley W. Terpstra
d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra
a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
Wesley W. Terpstra
b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip 
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
 2017-02-03 17:19:21 -08:00
Wesley W. Terpstra
fc9ea62d38 HeterogeneousBag: a handy container for differently parameterized bundles 2017-02-03 16:21:33 -08:00
Wesley W. Terpstra
7afe383db3 Ecc: detect uncorrectable errors also for SEC 2017-02-03 16:21:09 -08:00
Wesley W. Terpstra
7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
Wesley W. Terpstra
93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Jacob Chang
83a83c778a Added range function in IdRange 
Added source accessor function in TLEdge
 2017-02-02 12:35:57 -08:00
Andrew Waterman
8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN 
See https://github.com/riscv/riscv-isa-sim/issues/76
 2017-02-02 11:55:08 -08:00
Andrew Waterman
75edf42323 Set xPIE=1 on xRET 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
 2017-02-02 11:55:08 -08:00
Wesley W. Terpstra
9ca8f514c0 rocket: creating Bundles in an object also break dedup! 2017-01-31 14:45:11 -08:00
Wesley W. Terpstra
e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Wesley W. Terpstra
dc66c8857f diplomacy: be more robust using Java introspection 
If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
 2017-01-30 14:25:12 -08:00
Wesley W. Terpstra
280af9684b BankedL2Config: use the same LazyModule for all L2 banks 
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
 2017-01-30 14:02:59 -08:00
Wesley W. Terpstra
f7f52cc722 diplomacy: restore Monitor functionality 2017-01-29 17:25:14 -08:00
Wesley W. Terpstra
972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra
4d646939b0 diplomacy: make flexible-port adapters possible 2017-01-29 14:26:02 -08:00
Wesley W. Terpstra
24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
Wesley W. Terpstra
d5fa159063 diplomacy: add :*= and :=* to support flexible # of edges 2017-01-28 21:32:36 -08:00
Wesley W. Terpstra
03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
Wesley W. Terpstra
830d01329d RationalCrossing: add some documentation 2017-01-26 21:27:34 -08:00
Wesley W. Terpstra
fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra
5cf4b0632d RationalCrossing: clock crossing between related clock domains 2017-01-26 20:07:28 -08:00
Henry Cook
0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528) 2017-01-25 12:10:49 -08:00
Wesley W. Terpstra
6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra
46cdfc2b45 diplomacy: find names of LazyModules also in Seq() member values (#527) 2017-01-24 18:10:37 -08:00
Wesley W. Terpstra
3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
d4b3a0f0be diplomacy: support given bits in AddressDecoder 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
Wesley W. Terpstra
38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager 
This lets smart caches exclude the sets that are filtered.
 2017-01-21 13:23:07 -08:00
Wesley W. Terpstra
dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
Wesley W. Terpstra
9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
Wesley W. Terpstra
5d70265e86 rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra
bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Henry Cook
c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early 2017-01-19 17:48:04 -08:00
Henry Cook
e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
Henry Cook
307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Megan Wachs
e22b01a6fa jtag_dtm: Update regression to run and pass. 2017-01-18 12:08:13 -08:00
Henry Cook
9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513) 
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
 2017-01-17 11:57:23 -08:00
Henry Cook
74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Wesley W. Terpstra
52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) 
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
 2017-01-13 14:41:19 -08:00
Jacob Chang
59eb7c24ee Add iterator function to LazyModule to iterate over all nodes 2017-01-12 15:21:10 -08:00
Andrew Waterman
71c4b000b3 Don't special-case power-of-2 replacement policy for BTB 
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
 2017-01-11 13:21:55 -08:00
Jacob Chang
c531093898 Fix bug introduced with Fuzzer when nOperations is power of 2 (#492) 2016-12-15 19:10:53 -08:00
Wesley W. Terpstra
a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra
16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra
ed091f55e6 apb: diplomatic APB framework 2016-12-15 13:48:50 -08:00
Wesley W. Terpstra
a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Wesley W. Terpstra
9d50704b64 ahb: don't violate spec with SRAM fuzzing 2016-12-14 15:18:41 -08:00
Jacob Chang
2dd9e522a0 Merge branch 'master' into jchang_test 2016-12-12 20:02:53 -08:00
Henry Cook
540502f96d Convert frontend and icache to diplomacy/tl2 (#486) 
* [rocket] file capitalization

* [rocket] cacheDataBits &etc in HasCoreParameters

* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters

* [rocket] frontend and icache now diplomatic
 2016-12-12 17:38:55 -08:00
Jacob Chang
531f3684ed Removing module list for merging. (will need to create iterator in future) 2016-12-12 16:25:31 -08:00
Jacob Chang
aae9b23036 Update with paratermized LazyModule 2016-12-12 16:16:56 -08:00
Jacob Chang
762afcd54a Merge remote-tracking branch 'origin/master' into jchang_test 2016-12-09 16:56:49 -08:00
Jacob Chang
4c3083c181 Remove unnecessary val 2016-12-09 16:44:30 -08:00
Wesley W. Terpstra
09afbbafdb ahb: weaken RegisterRouter assertion 
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
588b944ed4 ahb: implement and test address decoding 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
5d1064fcb1 ahb: include a unit test 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
Wesley W. Terpstra
01b0f6a52b ahb: new diplomacy-based AHB bus definition 2016-12-08 18:00:39 -08:00
Jacob Chang
54cc071a64 Fix Fragmenter to ensure logical operations must be sent out atomically. 
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
 2016-12-07 16:22:05 -08:00
Wesley W. Terpstra
c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
Wesley W. Terpstra
020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Andrew Waterman
915697cb09 Fix FEQ flag generation (#479) 
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
 2016-12-06 11:54:29 -08:00
Wesley W. Terpstra
fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
Wesley W. Terpstra
3c9718ec8f clint: undefined registers must be zero (#480) 
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
 2016-12-05 17:11:53 -08:00
Henry Cook
f3d0692619 Make a directory for the config package (#464) 
* [config] make dir structure mirror packages

* [config] expunge max_int
 2016-12-05 10:42:16 -08:00
Henry Cook
d0a0c887dc [tracegen] decrease default address bag size (#462) 
while increasing the default number of requests.
 2016-12-04 22:46:55 -08:00
Schuyler Eldridge
36fe024671 CacheName no longer needed in RoCCInterface 
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
 2016-12-04 19:01:39 -08:00
Schuyler Eldridge
624db2034b Make instantiated RoCC use dcacheParams 2016-12-04 19:01:39 -08:00
Jacob Chang
cff2612cdb minor Changes needed to support formal tests 2016-12-01 15:02:23 -08:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
e2ec1d00ad copyright: normalize /// to // in comments 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
a0e10aec05 uncore: removed obsolete Builder file 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra
4146f6a792 TLB: do not access illegal addresses (#460) 2016-11-26 15:11:42 -08:00
Wesley W. Terpstra
a17753983a coreplex: allow legacy devices to override the config string (#458) 2016-11-25 19:38:24 -08:00
Wesley W. Terpstra
233280e7d2 AsyncBundle: save a wasted bit when depth=1 2016-11-25 18:11:01 -08:00
Wesley W. Terpstra
d755edffcc DebugTransport: use ToAsyncDebugBus for correct depth 2016-11-25 18:10:28 -08:00
Wesley W. Terpstra
2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) 2016-11-25 17:02:29 -08:00
Wesley W. Terpstra
1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) 2016-11-25 15:26:22 -08:00
Wesley W. Terpstra
0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong! 
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
 2016-11-24 18:32:44 -08:00
Wesley W. Terpstra
a670f63c81 periphery: a handy trait to turn-off ExtMem 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
566cc9e60b rocketchip: RTCPeriod config 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra
e87f54d4f7 rocketchip: traits for adding external TL2 ports 2016-11-23 20:44:42 -08:00
Wesley W. Terpstra
4b9dc78951 rocketchip: add a parameter-controlled debug port 2016-11-23 15:35:53 -08:00
Henry Cook
38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Henry Cook
dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook
c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Wesley W. Terpstra
1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00
Wesley W. Terpstra
1e7d597fd3 rocketchip: don't waste too many sources on the AXI master port 2016-11-22 21:48:41 -08:00
Wesley W. Terpstra
c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
Wesley W. Terpstra
0097274ea3 Broadcast: single-cycle response is possible 2016-11-22 20:45:40 -08:00
Wesley W. Terpstra
437be0f36a PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool)) 
This results in much less Verilog to simulate
 2016-11-22 20:39:38 -08:00
Wesley W. Terpstra
f9de7173cc PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) 2016-11-22 18:46:11 -08:00
Wesley W. Terpstra
d9a203b0f0 PositionalMultiQueue: convert 'next' to a single write port 2016-11-22 18:38:55 -08:00
Wesley W. Terpstra
13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c230580157 coreplex: rename RocketPlex => RocketTiles 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
bbabcf67ff coreplex: width adapter should happen as part of coherence manager 
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
a140b07009 rocketchip: cut coreplex from rocketchip 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra
c80ee06472 rocketchip: configString is a lazy property of outer 2016-11-22 17:27:58 -08:00
Andrew Waterman
5f3fb64ef0 Per ABI, only x1 and x5 should be treated as function returns 
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
 2016-11-22 12:01:05 -08:00
Wesley W. Terpstra
3d644b943c coreplex: configString is a property of the RISCVPlatform 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
e8be365b5d rocketchip: remove GlobalAddrMap completely 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
5fe107bb07 rocket: pass scratchpad address to block dcache 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
c18bc07bbc TLB: determine RWX from TL2 properties directly 2016-11-21 21:13:26 -08:00
Henry Cook
28c6be90ab [rocket] require refillcycesperbeat == 1 and remove flowthroughserializer 2016-11-20 19:36:51 -08:00
Henry Cook
ff9b5bf8fc [rocket] nbdcache release bugfix 2016-11-20 19:07:06 -08:00
Henry Cook
3f47d5b5eb [rocket] re-enable working NBDcache (passes Tracegen) 2016-11-19 19:19:16 -08:00
Henry Cook
c31b41a7ac [tl2] add grant finisher comment 2016-11-19 19:16:43 -08:00
Colin Schmidt
9dd12545d0 [Rocket] Send correct type for iomshr reqs 
Also contain grow param bugfix
 2016-11-19 19:04:06 -08:00
Wesley W. Terpstra
32a1c27441 rocket: disable nbdcache until it's fully ported 2016-11-18 19:55:24 -08:00
Wesley W. Terpstra
452bb2fc80 dcache fix TinyConfig 2016-11-18 19:50:34 -08:00
Wesley W. Terpstra
d1328a6b6f rocketchip: remove most uses of GlobalAddrMap 2016-11-18 19:38:02 -08:00
Henry Cook
2976fd84e4 [rocket] resolve cde/config conflicts 2016-11-18 19:11:34 -08:00
Henry Cook
8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
Henry Cook
5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
001d9821bd Merge remote-tracking branch 'origin/master' into tl2-tile 2016-11-18 18:19:41 -08:00
Wesley W. Terpstra
5b594ced29 Plic: support 0 interrupts gracefully 2016-11-18 18:07:44 -08:00
Wesley W. Terpstra
13ec3853ed junctions: get unit tests running again 2016-11-18 17:38:46 -08:00
Wesley W. Terpstra
10dd6070ad groundtest: gracefully handle zero uncached ports 2016-11-18 17:26:28 -08:00
Wesley W. Terpstra
03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
Wesley W. Terpstra
be8121eeaf coreplex: fix clock crossing 2016-11-18 17:15:57 -08:00
Wesley W. Terpstra
0082d713af coreplex: disable Stateless config until we implement adapter 2016-11-18 16:23:16 -08:00
Wesley W. Terpstra
8059d33217 groundtest: simplify FancyMemtestConfig for now 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
04b9a68ea6 MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
cd19bf65b8 regression: fix bad regression that deadlocks SoC with illegal D stall 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
5f7fa3dae5 regression: remove illegal test which reuses the same ID 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
40daea2e15 util: Config scheme supporting up with ++ 2016-11-18 16:18:30 -08:00
Wesley W. Terpstra
e5febcfa33 rocketchip: there are no more useful parameters to dump 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
119ccae9af rocketchip: don't use explicit cde namespace 2016-11-18 14:31:42 -08:00
Richard Xia
bab504cc3f Add various granular and composable configs. 2016-11-18 11:30:07 -08:00
Henry Cook
5bd343bac8 [rocket] d_last && d.fire() => d_done 2016-11-17 18:42:59 -08:00
Henry Cook
1ddccb1b33 [rocket] add TODO for single cycle ack 2016-11-17 18:42:59 -08:00
Henry Cook
94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
Henry Cook
960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
Wesley W. Terpstra
179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
Wesley W. Terpstra
f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
Wesley W. Terpstra
12d0d8bea2 rocketchip: remove obsolete bus configuration 2016-11-17 14:30:15 -08:00
Wesley W. Terpstra
c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
Wesley W. Terpstra
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
Wesley W. Terpstra
8a0ecdaaad groundtest: ComparatorConfig lives again 2016-11-17 11:07:49 -08:00
Henry Cook
92e233d596 [groundtest] testramaddr constant in package 2016-11-16 18:42:56 -08:00
Henry Cook
e1992d7c55 [rocket] grant addr bugfix 2016-11-16 18:12:06 -08:00
Henry Cook
84f249bd03 [rocketchip] BigInt cast 2016-11-16 18:11:06 -08:00
Henry Cook
da7ecfd189 [rocket] probeack vs probeackdata bugfix 2016-11-16 17:27:02 -08:00
Henry Cook
75d4347192 [groundtest] runs tests with new coreplex and top 2016-11-16 17:05:53 -08:00
Henry Cook
24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00
Henry Cook
408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
Henry Cook
1f51564577 [rocket] dcache probe ack data bugfix 2016-11-16 14:25:21 -08:00
Henry Cook
66a2c5544e [rocket] L1D acquire addr bugfix 2016-11-16 13:38:52 -08:00
Henry Cook
c5e03c9c76 [rocket] dcache release addr bugfix 2016-11-16 13:14:51 -08:00
Wesley W. Terpstra
06a7b95d0d tilelink2 broadcast: support bufferless Config 2016-11-16 12:25:11 -08:00
Wesley W. Terpstra
3703ed39f7 groundtest: PTW needs atomics 2016-11-16 12:16:54 -08:00
Wesley W. Terpstra
5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id 2016-11-16 12:16:25 -08:00
Wesley W. Terpstra
10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Henry Cook
2d68f12115 [tl2] give groundtest tile some output nodes 2016-11-14 18:09:40 -08:00
Wesley W. Terpstra
ab3dafb8bc Monitor: restore Probe&Acquire checks 2016-11-14 15:36:52 -08:00
Wesley W. Terpstra
385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
Henry Cook
0e30364f56 WIP 2016-11-14 13:39:01 -08:00
Henry Cook
c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) 2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
Wesley W. Terpstra
9d77e34bee tilelink2 Filter: make transfer cap robust against large filters 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
4a2cf6431b coreplex: make 'mem' port an Option until we can use a Seq 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
8f757a9135 coreplex: rename BankedL2 trait to BankedL2CoherenceManagers 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b tilelink2 Broadcast: support "bufferless" implementation 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4 tilelink2 Broadcast: only support caching readable devices 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
d03046d11c coreplex: fix BankedL2 line width 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
da3cc3b299 coreplex: TileLink2 l1tol2 memory channels 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
0f3947bb86 tilelink2 Broadcast: add special case handling for 0 cached clients 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f tilelink2 Xbar: merge the AddressSets of fractured managers 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb tilelink2: Filter adapter removes some of the address space 2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b tilelink2: broadcast coherence manager 2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager 2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
ed4224dde4 tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull 
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
 2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
f83d1d0aaf coreplex: rename trait CoreplexRISCVPlatform 
This makes it clear we are talking about the devices one expects in the
platform, not the ISA.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
f943c5d6ef rocketchip: connect rtcTick to coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
4a0b29850c coreplex: reattach clint interrupt 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
a12fea51e8 Plic: skip reserved interrupt in interrupt map printout 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
aabd17d935 rocketchip: must create bundles within Module scope 
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d52615c39e coreplex: one IntNode per tile 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e97844f71e coreplex: make it possible to override the ConfigString 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
4de1822470 rocketchip: avoid using the nearly defunct GlobalAddrMap 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
688e1bffdf rocketchip: pull rtcTick out of the coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d51b0b5c02 rocketchip: use self-type 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
841a31479a coreplex: fix TinyConfig 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
6505431eac coreplex: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
92ee498521 rocket scratchpad: support atomics 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616 regressions: test scratchpad 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d2e9fa8ec6 Plic: remove path from ready to bits 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7 Debug: mark the debug device executable 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
Wesley W. Terpstra
401fd378b4 rocketchip: include devices from cbus in ConfigString 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b68bc449e7 rocket: put a Fragmenter infront of the scratchpad 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
89139a9492 Plic: split constants from variables used in config string 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c rocket: convert scratchpad to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
dddb50a942 BuildTiles: convert to LazyTile 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
Megan Wachs
5090ff945b DebugModule: Be more paranoid about addressing corner cases. 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d PLIC: converted to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b Debug: make address configurable 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
Megan Wachs
10d084b9f3 DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f diplomacy: add BlindNodes for use as external ports 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
082f338432 diplomacy Nodes: remove useless indirection 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule 
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
Megan Wachs
af924d8c51 DebugModule: Instantiate TL2 DebugModule in BaseCoreplex 2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width 2016-10-31 11:41:18 -07:00
Howard Mao
f0e9a2a081 Fix PutBlock after Release bug 
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.

The fix is to make the outer release block if there are pending
inner PutBlock beats.
 2016-10-28 18:26:34 -07:00
Howard Mao
cb81ea516c add regression test for put-after-release bug 2016-10-28 18:26:34 -07:00
Howard Mao
fa8844d5c3 properly use rocket MT_ constants in regression tests 2016-10-28 18:26:34 -07:00
Andrew Waterman
e45b41b4b6 Don't rely on SeqMem output after read-enable is low 2016-10-27 23:44:10 -07:00
Howard Mao
900a7bbcf1 add PutAtomic support to width adapter 2016-10-26 09:58:26 -07:00
Jacob Chang
fc5eb7cc64 Fixed AsyncFifo with reset messaging 2016-10-25 16:45:08 -07:00
Megan Wachs
fd2d48acda lazy_module: If the user actually specifies a name, just use it without appending module name. 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
a807c922d0 diplomacy: take names from the outermost common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
fee67c4abf diplomacy: add methods to find {out,in}ner-most common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415) 
Sometimes we have high performance devices that go inbetween.
 2016-10-24 23:56:09 -07:00
Wesley W. Terpstra
a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417) 
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
 2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416) 
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
 2016-10-24 20:37:04 -07:00
Wesley W. Terpstra
8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Colin Schmidt
85f3788ab5 initialize s2_hit to solve #401 2016-10-21 14:53:55 -07:00
Wesley W. Terpstra
7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f axi4 Bundles: add a size calculation helper 
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9 tilelink2 Isolation: cross the valid signals as well 
Refactor the code to be less copy-pasty
 2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
680a944f07 regmapper RegisterCrossing: safe AsyncQueues are overkill here 2016-10-14 18:28:31 -07:00
Wesley W. Terpstra
ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue 2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
4e40f9bb59 tilelink2 Nodes: appease the PC police 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13 tilelink2 Nodes: include some options to test for conformance 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd tilelink2 Arbiter: there is only one winner 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f tilelink2 RegisterRouter: data path register is no longer required 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9 tilelink2: switch to DecoupledIO syntax 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
4c1c52486b axi4 Fragmenter: handle more inflight AXI requests than we have space 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131 axi4 Fragmenter: refine sideband FSM for case of last fragment 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b axi4 Fragmenter: align all output accesses 
We promised the output is aligned. Make good on that!
 2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3 axi4 Fragmenter: confirm correct handling of last 2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b axi4 Fragmenter: initialize error response to 0 2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba axi4 Fragmenter: optimize dynamic slave lookup 2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c axi4: add a Buffer to put between nodes 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e tilelink2 RAMModel: include name of test in output 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b axi4: include unit tests 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848 axi4: prototype Fragmenter 2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89 axi4: name AdapterNode parameters properly 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
38b6c1c820 tilelink2 axi4: RegisterRouter can cut ready dependency 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32 axi4 tilelink2: include minAlignment and maxAddress in slaves 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
538437384a tilelink2 Fragmenter: combine AccessAck errors 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
4caa543ad7 tilelink2: Fragmenter should not cut Acquire parameters 
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
 2016-10-11 22:38:03 -07:00
Wesley W. Terpstra
6336f94fa2 tilelink2: only caches can support B requests 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
4a975ca380 tilelink2: add a rightOR to go with our leftOR 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
b2a5d18e37 diplomacy: simplify address range fragmentation 2016-10-11 22:36:21 -07:00
Wesley W. Terpstra
b0e33f4a39 tilelink2: use TLArbiter in HintHandler 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
683a2e6785 tilelink2: refactor firstlast helper method 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
a404cd2abf tilelink2: use NodeHandle to restore Crossing.node API 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
876609eb0e diplomacy: add NodeHandles to support abstraction 2016-10-10 13:15:25 -07:00
Wesley W. Terpstra
97af07eb3e tilelink2: clarify use of Isolation 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
76388117bb regmapper: detect improper reset sequencing in RegisterCrossing 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
b5f5ef69c1 regmapper: eliminate race condition in RegisterCrossing bypass 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
f250426728 tilelink2: blow up if the channels carry data when they should not 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
1b09f1360d AsyncQueue: adjust register names to match vals 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
e7f8a7e9ea AsyncQueue: make it clear that the SyncChain is not Gray specific 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
52b8121e68 Apply "async_queue: Give names to all the registers which show up in the queue (#390)" 
Adjusted to include names for the new registers.
Changes to RegisterCrossing were discarded.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
ffb734ac0e AsyncQueue: disambiguiate the reset_n signal names 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
5ee53c61d6 util: clarify an AsyncQueue corner-case 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
609fd97a71 util: AsyncQueue detect power-down/reset of non-empty queue 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
75bb94017b util: resynchronize AsyncQueue counters when far side resets 
If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
5e2609bdd2 AsyncQueueSource: don't feed reset into normal logic! 
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
2f6985efd3 crossings: use flip not flip() 
This seems to be the more common API
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
6d6aa3eb13 tilelink2: Isolation must also connect reset_n 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
cb7b16f1a9 util: exchange resets between AsyncQueue source and sink 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
8c7d469a95 Revert "async_queue: Give names to all the registers which show up in the queue (#390)" 
This reverts commit a84a961a39.

The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
adf5f1807b tilelink2: ToAXI4 bridge added 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
e856cbe3a6 axi4: SRAM for testing 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
abb02aa6f4 axi4: add a RegisterRouter for generic devices 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
2f7081aeaf tilelink2: make mask generation reusable 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
b29d34038e axi4: diplomacy capable AXI4 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
dcb9383568 PositionalMultiQueue: work around vcs Lint report 
Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
  Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
  may need to be inout. Coercing to inout.
 2016-10-10 11:21:49 -07:00
Wesley W. Terpstra
5d905a5310 PositionalMultiQueue: shared storage FIFO 1-push n-pop 2016-10-10 11:21:49 -07:00
mwachs5
3a1d8fe482 debug: use a different form of the crossing which doesn't create an AsyncScope (#394) 2016-10-09 20:33:18 -07:00
mwachs5
b5d4b72313 register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. (#393) 2016-10-09 15:51:23 -07:00
Henry Cook
1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) 2016-10-09 12:34:10 -07:00
Andrew Waterman
53360f4c2c Disable U-mode by default unless S-mode is present 2016-10-08 21:29:40 -07:00
Andrew Waterman
7f429e8799 Simplify AsyncResetReg 
No need for AsyncSetReg, as AsyncResetReg can be used exclusively with
inverted inputs.
 2016-10-08 21:29:40 -07:00
mwachs5
a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) 
This is to aid debugging but even more so for backend constraint writers, who generally
need predictable names for registers to set false paths, etc.
 2016-10-08 17:50:50 -07:00
Andrew Waterman
4fd03ffdf1 Fix PopCountAtLeast, un-breaking BTB 2016-10-07 21:20:40 -07:00
Wesley W. Terpstra
e5ac0f717f tilelink2: split isolation gates by direction 2016-10-07 12:03:43 -07:00
Albert Ou
ad618fd55d plic: Fix bit extraction 2016-10-06 18:05:03 -07:00
Andrew Waterman
b1c777c7a2 Fix PLIC enable bit access for #ints >= tlDataBits 2016-10-06 16:21:14 -07:00
Andrew Waterman
c22438b822 Fix an overly strict D$ assertion 2016-10-06 15:52:46 -07:00
Jacob Chang
fe641c14a1 tilelink2: Add support for different noise generator in fuzzer (#386) 2016-10-06 13:20:13 -07:00
Andrew Waterman
5980dc160f Don't allow multiple entries for same PC in BTB 
Necessary for RVC forward-progress guarantee.
 2016-10-06 11:30:45 -07:00
Andrew Waterman
eddf1679f5 Use <> instead of := for bi-directional connections 2016-10-04 22:29:39 -07:00
Andrew Waterman
67593fdf2d Explicitly zap some S-mode CSRs when not using S-mode 2016-10-04 22:29:39 -07:00
Andrew Waterman
968851f7e3 Default to configurable priorities 
up-to-7 levels is kind of arbitrary, but I'm unwilling to introduce
a new Parameter at the moment.
 2016-10-04 22:29:39 -07:00
mwachs5
e952f8f222 asyncqueue: Fix typo in the Async Queue (#381) 
* asyncqueue: Fix typo in the Async Queue that would cause the sync depth to be one less than expected.

* asyncqueue: Typo in the typo fix
 2016-10-04 21:02:06 -07:00
Andrew Waterman
064c9ebdc6 Don't report I$ fetch faults on TLB misses! 2016-10-04 14:37:25 -07:00
Andrew Waterman
516481b68b Improve back-to-back integer multiplication performance 
More exact hazard checking in the decode stage avoids a pipeline flush.
 2016-10-04 14:37:25 -07:00
Andrew Waterman
7b69f1f261 Don't enter D$ flush state machine if grant outstanding 2016-10-04 14:37:25 -07:00
Andrew Waterman
28beb33943 Make any intervening load/store/fence fail an LR/SC sequence 
This catches LR/SC misuses more quickly.
 2016-10-04 14:37:25 -07:00
Yunsup Lee
62954d543e correctly initialize the active flag 2016-10-03 17:56:30 -07:00
Wesley W. Terpstra
6ec2e7c5bd tilelink2: Legacy should preserve the access size (#378) 
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
 2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303 tilelink2: Nodes should accept full PortParameters 
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
 2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf graphML: CTO's like colour 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084 LazyModule: output final verilog Module name 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff tilelink2 RegisterRouter: test fully Decoupled behaviour 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
422e6357a4 tilelink2 RegisterCrossing: Queues go from RV to Irrevocable 
AsyncQueue is still a Queue.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
02f89fb530 RegMapper: clarify interface is DecoupledIO 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad tilelink2 RegField: clarify restrictions on functions 
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
 2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428 tilelink2 RegisterRouter: fix output data glitches 
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
 2016-10-02 02:24:02 -07:00
Andrew Waterman
e0188f8aa4 Don't implicitly fence on CSR instructions 
CSRs that have an effect on I/O should use an explicit FENCE.
 2016-10-01 19:44:10 -07:00
Andrew Waterman
b772edcb1b Allow hit-under-MMIO and multiple MMIOs in blocking D$ 
The latter feature is by default disabled, since there aren't enough
ID bits.
 2016-10-01 19:44:05 -07:00
Megan Wachs
28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a tilelink2 Isolation: add enable signal (#368) 2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193 tilelink2: Isolation gate insertion module 2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52 tilelink2 Crossing: helpful constructor objects 2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3 tilelink2: helper objects operate on OutwardNodes 2016-09-30 01:39:35 -07:00
Howard Mao
4b86802b1a change the configuration interface of SlowIO 2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains 2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c tilelink2: add types for a TL clockless interface 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831 tilelink2: rename BaseNode to SimpleNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves 
This lets us create nodes which transform from one bus to another.
 2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce Default mtvec=0, not None 
Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
 2016-09-29 13:52:41 -07:00
Megan Wachs
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
Henry Cook
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry Cook
32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9 [tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356) 2016-09-27 18:06:21 -07:00
Howard Mao
c45cc76cef Get rid of remaining MemIO code 
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
 2016-09-27 16:28:17 -07:00
Howard Mao
18e7ea89f2 Get rid of broken groundtests 
The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.

The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.
 2016-09-27 16:28:17 -07:00
Howard Mao
c77c244016 Get rid of NASTI memory interconnects 
These were made for a previous Hurricane tapeout, but we are now doing
all of the memory routing in TileLink, so they are no longer needed.
 2016-09-27 16:28:17 -07:00
mwachs5
f9e0a7ac24 Merge branch 'master' into async_register_crossing 2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
3926cb936b rocketchip: add pbus width and AMO With classes (#357) 2016-09-27 15:52:13 -07:00
Wesley W. Terpstra
eaea138d0d tilelink2: don't use chisel3 namespace (#355) 2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab Merge branch 'master' into async_register_crossing 2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c tilelink2 WidthWidget: Gets must have their mask adjusted (#353) 
The mask of a Get should also be converted.

This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
 2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5 crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations 2016-09-27 13:36:28 -07:00
Howard Mao
71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
Howard Mao
7d6fb950b6 Give TileLink IDs more sensible names 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
 2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01 move memory width adapter from coreplex to periphery 2016-09-27 12:48:01 -07:00
Howard Mao
e36441a046 use correct parameters object for MMIO width adapter 2016-09-27 12:48:01 -07:00
Howard Mao
201e247f73 Factor coreplex IO connection into separate trait (#350) 
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
 2016-09-27 11:55:32 -07:00
Howard Mao
6316ebd58f make naming of L2toMC parameter object consistent between coreplex and periphery 2016-09-26 17:28:21 -07:00
Howard Mao
ea9f0a868f TileLink utility objects should not take implicit parameters 
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
 2016-09-26 17:28:21 -07:00
Howard Mao
803739a95c Make sure coreplex mmio's TLId is correct (thanks to zizztux) 2016-09-26 17:28:21 -07:00
Howard Mao
c741ada619 get TraceGen working again 2016-09-26 17:28:21 -07:00
Wesley W. Terpstra
d9e209365d Tl2 addr width0 (#346) 
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}

* tilelink2: use addr_lo instead of relying on truncation

Truncation can mess up if the width should be 0, but IS 1.
 2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f tilelink2 AddressSet: add .misaligned(low, size) helper method (#345) 
This helps devices with misaligned ranges still connect to TL2.
 2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
1773eb4405 tilelink2 LazyModule: output GraphML of the bus 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc tilelink2 Nodes: expose connectivity in RootNode 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
14cd39e045 rocketchip: rename identically names devices with _%d (#340) 
* rocketchip: rename identically names devices with _%d

If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...

* junctions: blow if duplicates add to addrmap
 2016-09-26 13:05:49 -07:00
mwachs5
77a0f76289 Cleanup jtag dtm (#342) 
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
 2016-09-26 11:10:27 -07:00
mwachs5
8641639873 Async rst async queue (#336) 
* crossing: use async reset

* crossings: asyncqueue needs Asynchronous reset.

* crossing: Actually enable the head of the synchronizer flop chain

* crossing: remove reset from logic. This flop will no longer be written during reset because valid will be low.

* crossing: Tidy up code  & comments
 2016-09-26 11:08:38 -07:00
Wesley W. Terpstra
d787bae0d0 tilelink2 Xbar: decouple ready from valid (#338) 
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
 2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) 2016-09-23 15:25:58 -07:00
Wesley W. Terpstra
47843d8ec1 tilelink2: maxLgSize should be accurate (#332) 2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11 RegField: remove obsolete split method 
This is now natively supported by the regmap(...) invocation.
 2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10 RegField: add name and description fields 
In the future we can generate interesting documentation and headers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee RegMapper: regmap(...) now takes BYTE addresses 
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.

This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729 RegField: remove RegField.bytes; it was dangerous 
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node) 
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
 2016-09-22 20:52:46 -07:00
Howard Mao
22053289ef fix typo rv64iu -> rv64ui 2016-09-22 17:33:35 -07:00
Henry Cook
673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
Henry Cook
1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook
391be8d740 tilelink2 RegisterRouter: minLatency is never more than 1 2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a tilelink2 Atomics: optimize the sign-extension circuit 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
9f1f6fc61f Comparator: tolerate mismatched data when it is undefined 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef tilelink2 Fuzzer: work around for firrtl/verilator performance issue 
Big Vec()s cause very slow compilation.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue 
Big Vec()s cause problems for these tools.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31 tilelink2 Legacy: convert TL1 atomic operand size 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb tilelink2 Atomics: support arithmetic atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51 tilelink2 Atomics: support Logical AMOs 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9 tilelink2 Atomics: exploit minLatency to eliminate bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223 tilelink2 Monitor: detect minLatency violations 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4 tilelink2: most adapters can wipe away latency 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624 tilelink2 Buffer: increase the minLatency on ports 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e tilelink2 Fuzzer: test Atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d tilelink2 RAMModel: support (by ignoring) atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a tilelink2 AtomicAutomata: prototype flow control complete 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa tilelink2: add a general-purpose Arbiter 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8 tilelink2 Fuzzer: only generate legal atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics 
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves 2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b tilelink2 Bundles: add 1-way snoop bundles 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled 2016-09-22 15:14:19 -07:00
Henry Cook
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook
47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Albert Ou
d76b762657 tilelink2 Fragmenter: Mask low bits of D channel addr_lo 
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
 2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Howard Mao
cbd702e48e make sure junctions and uncore unittests both run 2016-09-21 20:17:52 -07:00
Yunsup Lee
1b1ef3be07 simplify base Coreplex bundle 2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Henry Cook
64fe010369 [unittest] Config import tweaks 2016-09-21 17:40:39 -07:00
Henry Cook
fd5e00fed9 [coreplex] rename Testing.scala -> RocketTestSuite.scala 2016-09-21 17:35:39 -07:00
Henry Cook
270011b768 [unittest] more Config cleanup 2016-09-21 17:30:14 -07:00
Yunsup Lee
7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Andrew Waterman
8e63f4a1a5 Remove ClockToSignal and vice-versa 
Clock.asUInt and Bool.asClock now suffice.
 2016-09-21 16:17:14 -07:00
Henry Cook
335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Andrew Waterman
12d0c00822 Fix mtime RegField handling 
RegField.bytes was unconditionally overwriting mtime, preventing it
from ever ticking.  Avoid RegField.bytes by splitting mtime into
a Seq of words.
 2016-09-20 15:00:52 -07:00
Henry Cook
40f6f31611 [unittest] further refactor unittest framework 2016-09-20 14:14:30 -07:00
Henry Cook
ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
Henry Cook
b97a0947a9 [rocketchip] enable piecewise Generator output 2016-09-20 12:57:56 -07:00
Yunsup Lee
1a09e46f69 Merge branch 'master' into fix-addrmap-error-msg 2016-09-19 18:08:58 -07:00
Andrew Waterman
3b38736a8e Make BaseTopModule and BaseTopModule abstract 
They aren't meant to be directly instantiated.
 2016-09-19 17:18:35 -07:00
Andrew Waterman
d0572d6aab Allow reset vector to be set dynamically 
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
 2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd Expose carry-out bits from WideCounter 2016-09-19 15:54:17 -07:00
Yunsup Lee
1b26d78114 correctly print out the addrmap overlapping error message 2016-09-19 13:34:58 -07:00
Henry Cook
df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Henry Cook
7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00
Andrew Waterman
a49814c667 Allow WideCounter to not be reset 2016-09-18 18:45:51 -07:00
Wesley W. Terpstra
9817a00ed9 tilelink2: Fuzzer should check address validity before injection 2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1 tilelink2: differentiate fast/safe address lookup cases 2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214 tilelink2: minimize Xbar decode logic 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c tilelink2: consider the implications of negative address mask 2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548 tilelink2: track interrupt connectivity like in TL2 2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
01c1886b9d Utils: cacheable only if there is a cache manager 2016-09-17 00:56:21 -07:00
Wesley W. Terpstra
6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
e749558190 ROM: optionally (default: true) executable 2016-09-17 00:19:09 -07:00
Wesley W. Terpstra
c70045b8b3 Utils: express cacheability from TL2 to TL1 2016-09-17 00:16:40 -07:00
Wesley W. Terpstra
e3d2bd3323 Top: print memory region properties, RWX [C] 2016-09-17 00:16:00 -07:00
Wesley W. Terpstra
5c858685aa Utils: support managers with multiple addresses 2016-09-16 18:03:49 -07:00
Richard Xia
3fdf40c088 Change implicit argument to explicit. 2016-09-16 17:47:31 -07:00
Wesley W. Terpstra
a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
Wesley W. Terpstra
b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Richard Xia
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
Wesley W. Terpstra
dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
Andrew Waterman
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter 
That's all it's doing (there wasn't much PRC).
 2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
mwachs5
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Wesley W. Terpstra
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
Henry Cook
851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports 2016-09-15 14:25:47 -07:00
Henry Cook
245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
Henry Cook
a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor 2016-09-15 13:27:07 -07:00
Henry Cook
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00
Henry Cook
888f6a2a55 Revert "move UnitTest back into rocketchip module" 
This reverts commit f95b8c4ec2.
 2016-09-15 11:48:09 -07:00
Henry Cook
0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook
ab3814dcee Merge branch 'master' into tl2-irrevocable 2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Wesley W. Terpstra
1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881 [junctions] messed up the merge lulz 2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook
08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman
5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) 2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao
1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook
632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Henry Cook
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Wesley W. Terpstra
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Wesley W. Terpstra
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00
Wesley W. Terpstra
cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
Wesley W. Terpstra
1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Wesley W. Terpstra
66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Wesley W. Terpstra
60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Yunsup Lee
2c000a99da compartmentalize Top into periphery traits 2016-09-08 02:08:57 -07:00
Yunsup Lee
e35e7b2ee3 Fix routing in non-contiguous MMIO regions 
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
 2016-09-07 19:28:12 -07:00
Andrew Waterman
7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Colin Schmidt
254f49093c only use companion objects for types 2016-09-07 12:32:34 -07:00
Andrew Waterman
23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
Andrew Waterman
02a2439222 Support a degenerate PLIC with no interrupts 
Resolves #249
 2016-09-07 11:21:13 -07:00
Andrew Waterman
70cfd7ce13 Make DefaultRV32Config be RV32IMAFCS, not RV32IMC 
The latter is more the domain of TinyConfig.
 2016-09-07 01:58:25 -07:00
Andrew Waterman
a7f47f3c23 Reduce default BTB size 
The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a.  The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
 2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0 Add MuxT to mux on Tuple2 and Tuple3 2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5 Evaluate arg to Boolean.option lazily 2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80 avoid erroneously setting tags valid during flush 2016-09-07 00:05:38 -07:00
Yunsup Lee
fb05f5a07f remove parameter ExtIOAddrMapEntries (#250) 
with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
 2016-09-07 00:05:00 -07:00
Wesley W. Terpstra
d2421654c4 tilelink2: refactor address into addr_hi on ABC and addr_lo on CD 
We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
 2016-09-06 23:46:44 -07:00
Yunsup Lee
b76612f357 relax contraint on adding AddrMapEntry to AddrMap (#248) 
now you can add them in any order.  there's an explicit check at the end to figure out whether there are overlapping regions.
 2016-09-06 21:53:55 -07:00
Wesley W. Terpstra
aae4230627 tilelink2: fix bugs found by Megan in Legacy converter 2016-09-06 13:12:33 -07:00
Yunsup Lee
56d81b0034 fix configstring printout with no memory 2016-09-06 10:40:11 -07:00
Wesley W. Terpstra
54ab14cd9d tilelink2: statically optimize numBeats for simple managers 2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f tilelink2: stricter TransferSizes requirements 2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c tilelink2: be more forgiving in what Legacy TL requires 2016-09-05 21:12:51 -07:00
Wesley W. Terpstra
3167539331 tilelink2: Narrower must be little-endian 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
ded246fb95 tilelink2: relax max transfer size; the real requirement is not exceeding alignment 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cf0291061d tilelink2: fix a bug in UIntToOH1 triggered if the size was too big 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
9f45212c95 tilelink2: Fragmenter needs to update subaddress 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
757d46279e tilelink2: expand data correctly in D channel narrower 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
0faa8c4051 tilelink2: fix Xbar bug where Mux1H broke FSM if only one manager 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
a0c25880c7 tilelink2: Monitor should check mask of reconstructed request 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
df32cc3887 tilelink2: be careful; apply Andrew's masking trick everywhere 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
fb262558ee tilelink2: helper objects should pass source line from where they were invoked 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
1a081b4dd5 tilelink2: Monitor should report which TL connection was the problem 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
cb54df0a8a tilelink2: tie off unused channels 2016-09-05 20:58:41 -07:00
Wesley W. Terpstra
68e64a9859 tilelink2: clarify ready-valid use of RegisterRouter 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e3b3543841 tilelink2: ensure RegFields don't exceed their bounds 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
8343070639 tilelink2: detect 1-bit overflow in register definitions 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
a1fc01fd6d tilelink2: prevent mapping the same register twice 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
81162a2dc9 tilelink2: support attaching a DecoupledIO directly to a register 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
6a378e79e3 tilelink2: allow 0-stage backpressure in combinational regmap 2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4746cf00ce tilelink2: move files to new uncore directory 2016-09-05 20:58:40 -07:00
Howard Mao
a7f79aa409 get rid of TileLinkMemorySelector 2016-09-04 10:55:19 -07:00
Howard Mao
f0ab6d0214 tie off finish signals in tilelink wrapper and unwrapper 2016-09-04 10:55:19 -07:00
Howard Mao
66de89c4db allow fixed priority routing in Junctions arbiters 2016-09-04 10:55:19 -07:00
Howard Mao
efe8670283 allow Serializer/Deserializer to work with arbitrary Chisel data types 2016-09-04 10:55:19 -07:00
Howard Mao
b9b79e4fb6 get rid of AtoS RTL 2016-09-04 10:55:19 -07:00
Howard Mao
f34843f1b9 fix assignment of incoherent vector 2016-09-04 10:12:16 -07:00
Yunsup Lee
a4c1942958 flatten Coreplex module hierarchy 2016-09-02 17:45:08 -07:00
Andrew Waterman
63679bb019 Add support for L1 data scratchpads instead of caches 
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
 2016-09-02 16:22:07 -07:00
Jim Lawson
dc9ae19936 Work-around for current Scala compiler "structural type loses implicits". 
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.

    [error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
    [error] possible cause: maybe a semicolon is missing before `value asOutput'?
    [error]   }.asOutput
    [error]     ^
    [error] one error found
    [error] (uncore/compile:compileIncremental) Compilation failed

This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
 2016-09-02 15:38:18 -07:00
Andrew Waterman
fb50f7c9dd Set default TileLink width to XLen 2016-09-02 15:27:54 -07:00
Andrew Waterman
e23e4d6de5 Add ClientUncachedTileLinkEnqueuer utility 2016-09-02 15:27:54 -07:00
Andrew Waterman
7aeb42fa55 Allow narrow TL interface on PRCI; make mtime writable 2016-09-02 15:27:54 -07:00
Andrew Waterman
6872000f5e Merge pull request #239 from ucb-bar/move_rtc 
Move RTC
 2016-09-02 15:17:49 -07:00
Megan Wachs
af364bc7bc Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal 2016-09-02 15:14:39 -07:00
Megan Wachs
8163a6b597 Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications 2016-09-02 11:11:40 -07:00
Andrew Waterman
c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Yunsup Lee
4a7972be31 connect testharness components via member functions (#236) 
to prevent code duplication for new testbenches
 2016-09-01 18:38:39 -07:00
Howard Mao
c66318307c no longer need to set invalidate_lr in RoCC examples 2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c tie off invalidate_lr in RoCC 2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8 don't override req.bits.phys in SimpleHellaCacheIF 2016-08-31 22:00:27 -07:00
Howard Mao
50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4 fix DecoupledTLB to handle misses appropriately 2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
SeungRyeol Lee
b1ce3b8c98 Add address map entries for exported mmio port. 2016-08-31 06:58:38 +09:00
Andrew Waterman
8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
Andrew Waterman
07d48df88a Get rid of FPU RoCC port logic when RoCC not present 
The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC.  Thus, when the RoCC was not
present, it was still creating muxes.  Using ex_cp_valid instead
gets rid of them.
 2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
Andrew Waterman
9ca82dd397 reset default MulDiv config to moderately fast default 
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
 2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60 set missing port direction 
Ideally, chisel should flag this as an error.
 2016-08-29 12:31:52 -07:00
Megan Wachs
53ee54dbd1 Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself 2016-08-26 10:40:39 -07:00
Megan Wachs
41aa80c5d7 Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts 2016-08-26 09:32:36 -07:00
Ben Keller
79293f4fa2 Use a better iterator inside the DCache 2016-08-25 20:41:39 -07:00
Henry Cook
115e8edd83 Merge branch 'master' into coreplex_peripheral_interrupts 2016-08-25 17:26:56 -07:00
Henry Cook
93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
Megan Wachs
428eed79a1 Allow some External Interrupts to come from Periphery 2016-08-25 14:16:33 -07:00
Megan Wachs
32118269c1 Remove } introduced in merge 2016-08-23 08:20:52 -07:00
Megan Wachs
9974626d6a Merge remote-tracking branch 'origin/master' into HEAD 
Conflicts:
	src/main/scala/rocketchip/TestHarness.scala
 2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44 fix bus axi connections in periphery 2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2 extra devices should get elaborated in a single build function 2016-08-22 11:57:15 -07:00
Scott Johnson
96e2cefb34 Merge branch 'master' into HEAD 2016-08-22 11:37:30 -07:00
mwachs5
22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
Megan Wachs
75efc7dee7 JtagIO's DRV_TDO should be an INPUT 2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb Move files after the file reorganization 2016-08-19 16:11:41 -07:00
Megan Wachs
3dd51ff734 This commit adds Logic & test support for JTAG implementation of Debug Transport Module. 
- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0
 2016-08-19 16:08:31 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation 
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
 2016-08-19 16:08:17 -07:00
Howard Mao
f4e0e0966c move rocketchip package sources into its own subdirectory 2016-08-19 13:45:23 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
Andrew Waterman
114226252b Hierarchicalize D$ config 2016-08-19 12:12:34 -07:00
Andrew Waterman
3f8c60bbd6 Hierarchicalize FPU and MulDiv parameters 
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
 2016-08-19 12:06:17 -07:00
Colin Schmidt
0a6c05a5d8 connect top level interrupts to coreplex 2016-08-18 15:52:44 -07:00
Howard Mao
91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao
1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao
18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao
f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao
d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
David Biancolin
29600f64ec make memsize configurable 2016-08-17 16:31:34 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Howard Mao
47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao
e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao
4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao
0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao
3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Howard Mao
9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao
410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Howard Mao
f04aefc95c get rid of deprecated ZynqAdapter 2016-08-02 13:14:20 -07:00
Howard Mao
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao
b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao
98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Megan Wachs
55c992bb3a Use FoldRight() instead of for loop 2016-08-01 16:56:33 -07:00
Megan Wachs
8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman
058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Howard Mao
cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Howard Mao
ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao
1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao
75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Megan Wachs
c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Howard Mao
20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Wesley W. Terpstra
9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Howard Mao
e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42 Rename MulDivUnroll to MulUnroll 2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96 Create seperate Mul/Div paramters instead of UseFastMulDiv 2016-07-15 14:40:37 -07:00
Andrew Waterman
ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Howard Mao
90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao
f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao
74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4 make Comparator fit the GroundTest model 2016-06-27 16:01:32 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao
3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
ff43238e6e give DualCoreConfig L2 cache to speed up test runs 2016-06-20 17:58:26 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b return non-zero exit codes when an assertion fires 
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
 2016-05-18 12:57:58 -07:00
Andrew Waterman
684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Andrew Waterman
6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao
dfcb73b6c9 groundtest only needs to write to a single tohost 2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5 fix CacheFillTest 2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa add default cases to configs that use CDEMatchError 
this avoids filling in the stack trace every time
a config doesn't contain the parameter
 2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969 put memory into the address map and no longer use MMIOBase 2016-04-21 18:53:16 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs 
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
 2016-04-12 15:39:15 -07:00
Andrew Waterman
b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. 2016-04-01 18:09:00 -07:00
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao
1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
d697559754 Correct the polarity of the non-backup-memory HTIF 
This fails in FIRRTL because <> has polarity now.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
c989ec5813 Fix the SCR file for Chisel 3 2016-03-21 11:55:40 -07:00
Howard Mao
e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Eric Love
4fc2a14a63 Fix MIF bug that cuts off upper xact id bits 2016-03-16 13:50:30 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Andrew Waterman
7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao
5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata 
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
 2016-03-01 13:03:24 -08:00
John Wright
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64 
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
 2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781 Add an 8-channel backup memory port config 
Now that the backup memory port works I want to test it.
 2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0 Fix the backup memory port on multiple-channel configs 
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
 2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port 
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
 2016-02-27 10:46:56 -08:00
Yunsup Lee
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
Colin Schmidt
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/... 
This uses the compiled tests in RISCV, which match the rest of the toolchain.
 2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
Colin Schmidt
0c575403af only use a single asm test and 1 bmark for memtest 2016-02-22 09:36:53 -08:00
Howard Mao
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab Allow the number of memory channels to be picked at runtime 
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
 2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Christopher Celio
c1b4d9372f Revert "add new parameters for new SCR file" 
This reverts commit 4dad5b8b32.

The commit breaks the build.
 2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a Revert "use singleton for global" 
This reverts commit 4d0f941de3.

The commit breaks the build.
 2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3 use singleton for global 2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes 
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
 2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one 
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
 2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao
c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Howard Mao
806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao
8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Howard Mao
0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao
f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao
cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Howard Mao
c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
Howard Mao
40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao
23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Howard Mao
ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Andrew Waterman
5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao
149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity 2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b fix NSets calculation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674 add 2 and 4 memory channel configs 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao
eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Howard Mao
c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609 L2 rowBits param bugfix 2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale) 2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) 2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5 Merge branch 'param-refactor-tl' 2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Christopher Celio
c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Andrew Waterman
700910adff Chisel3 compatibility fix for <> 2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6 Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7) 2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). 
Bump all submodules.
 2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d add zscale programs 2015-07-27 19:06:06 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Yunsup Lee
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Yunsup Lee
4c7c3f5bb2 add test generate for ZscaleTop 2015-07-14 16:26:28 -07:00
Henry Cook
76046c52fe Cleanup testing rv64uf 2015-07-13 18:58:58 -07:00
Henry Cook
302cd3e638 Added BuildZscale param for use in Top and makefrag generation 2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d rename Configs source 2015-07-09 15:04:11 -07:00
Yunsup Lee
09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff Added some multicore/multibanks named ChiselConfigs 2015-07-06 18:21:06 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Yunsup Lee
702ddabe26 add ExampleSmallConfig for README 2014-10-07 02:07:59 -07:00
Yunsup Lee
e25d420155 Improve ChiselConfig composability; bump chisel 2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65 Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays) 2014-10-06 13:40:35 -07:00
Henry Cook
122733b3a9 file name consistency 2014-10-06 13:37:38 -07:00
Henry Cook
0b5f23a209 Streamlined uncore for release 2014-10-06 13:37:15 -07:00
Adam Izraelevitz
15fb4730ec Add BuildTile parameter for Tile 
Conflicts:
	rocket
 2014-09-25 06:50:45 -07:00
Henry Cook
7398b00d93 dir supplied by function 2014-09-25 06:50:41 -07:00
Henry Cook
5a840c5520 support for multiple tilelink paramerterizations in same design 2014-09-25 06:50:30 -07:00
Donggyu Kim
eb384f6461 new RocketChipBackend implementation 2014-09-25 06:47:12 -07:00
Scott Beamer
f2ca887de3 better fpga configs 2014-09-25 06:47:03 -07:00
Donggyu Kim
4fe48f5a0a bump chisel 2014-09-25 06:46:58 -07:00
Donggyu Kim
60d90f5230 recover collectNodesIntoComp in Backends.scala 2014-09-25 06:46:50 -07:00
Donggyu Kim
a53091b40f remove collectNodesIntoComp from Backends.scala 2014-09-25 06:46:27 -07:00
Scott Beamer
f4e6cd75ab turn off fpu for default fpga config. 
a larger fpga can use defaultconfig
 2014-09-25 06:46:16 -07:00
Yunsup Lee
09de2e2794 compute number of outstanding misses for DRAMSideLLCNull 2014-09-12 18:09:38 -07:00
Yunsup Lee
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee
c98afa1fea turn off DRAMSideLLC 2014-09-11 22:10:25 -07:00
Yunsup Lee
b5a64487eb turn off DRAMSideLLC 2014-09-11 22:07:44 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
6b6bdd2b83 decommission Slave top-level module for fpga build 2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Henry Cook
ae05125f29 Adjustements to top-level parameters and knobs for hwacha 2014-09-07 17:57:33 -07:00
Henry Cook
4126678c9d Merge branch 'dse' 
Conflicts:
	rocket
	uncore
 2014-09-06 06:59:14 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Yunsup Lee
7734285507 forgot to comment out hwacha 2014-09-01 09:01:36 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Henry Cook
78ab83d224 refactor fpga top/config 2014-08-28 13:07:54 -07:00
Henry Cook
bf356b9cb4 Refactor to combine fpga and vlsi tops, part 1 2014-08-24 19:30:53 -07:00
Henry Cook
a41d55b643 Final parameter refactor. 2014-08-23 01:26:03 -07:00
Scott Beamer
63b62394d9 added l2 to fpga 
with new chisel & uncore, it goes into brams
 2014-08-20 15:41:07 -07:00
Henry Cook
1563c1bb36 Fixed cache params. Asm and bmark tests pass. 2014-08-12 15:00:54 -07:00
Henry Cook
7f07771600 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Adam Izraelevitz
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Henry Cook
434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Henry Cook
ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00
Henry Cook
fbf6e44376 fix connection error in fpga uncore 2014-04-24 11:58:59 -07:00
Henry Cook
cfd6748318 patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) 2014-04-21 17:26:33 -07:00
Henry Cook
2cb4dbae39 Refactored uncore constants and tilelink data 2014-04-10 13:19:50 -07:00
Henry Cook
5a5f69bfca finished uncore constant/tilelink data refactor 2014-04-10 13:13:46 -07:00
Andrew Waterman
817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Henry Cook
56f515c255 first steps in uncore constant/tilelink data refactor 2014-03-30 09:21:08 -07:00
Andrew Waterman
d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Yunsup Lee
e20d50436a committed in the wrong directory, meant to commit in the hwacha directory 2014-03-01 00:01:35 -08:00
Yunsup Lee
8c459df3b6 flush deck when xcpt occurs, fixes remaining p test bugs 2014-02-28 22:50:34 -08:00
Stephen Twigg
755293d785 Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha). 2014-02-14 10:12:09 -08:00
Andrew Waterman
11e69a73cd Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
Stephen Twigg
8c96e27ca6 Merge branch 'master' into hwacha-port 
Mostly Stable version that is passing tests
 2014-02-04 17:20:28 -08:00
Henry Cook
382fa0ef27 cleanups supporting uncore hierarchy 2014-01-31 16:03:58 -08:00
Stephen Twigg
e7ee94bcc8 Merge branch 'master' into hwacha-port 2014-01-21 15:23:05 -08:00
Stephen Twigg
ee0c4ca291 Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) 2014-01-21 14:48:04 -08:00
Andrew Waterman
6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman
a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Stephen Twigg
e50c5180cd Merge branch 'master' into hwacha 2013-11-14 16:03:55 -08:00
Yunsup Lee
1d6d4b4e96 move htif to uncore 2013-11-07 13:19:19 -08:00
Yunsup Lee
c810847761 hookup all memory ports 2013-11-05 17:12:25 -08:00
Stephen Twigg
7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
Stephen Twigg
36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Huy Vo
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Andrew Waterman
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook
b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
Stephen Twigg
6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Yunsup Lee
ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee
76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee
0884bc9789 fix DRAMSideLLCNull entries 2013-08-24 13:20:38 -07:00
Yunsup Lee
1e3ac0afa9 back to NTILES=1 2013-08-24 13:10:30 -07:00
Henry Cook
b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook
85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Henry Cook
6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
 2013-08-15 16:39:30 -07:00
Henry Cook
784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook
9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Huy Vo
cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Henry Cook
11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook
199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00