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c80ee06472
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rocketchip: configString is a lazy property of outer
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2016-11-22 17:27:58 -08:00 |
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5f3fb64ef0
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Per ABI, only x1 and x5 should be treated as function returns
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
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2016-11-22 12:01:05 -08:00 |
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42b40130e2
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Merge pull request #443 from ucb-bar/tl2-tlb
Tl2 tlb
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2016-11-21 22:00:30 -08:00 |
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3d644b943c
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coreplex: configString is a property of the RISCVPlatform
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2016-11-21 21:13:26 -08:00 |
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e8be365b5d
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rocketchip: remove GlobalAddrMap completely
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2016-11-21 21:13:26 -08:00 |
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5fe107bb07
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rocket: pass scratchpad address to block dcache
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2016-11-21 21:13:26 -08:00 |
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c18bc07bbc
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TLB: determine RWX from TL2 properties directly
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2016-11-21 21:13:26 -08:00 |
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3d1a7bd6d3
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travis: build verilator and toolchain as part of install
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2016-11-21 21:13:26 -08:00 |
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ea3ec89676
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travis: split RocketSuite into three smaller tests suites
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2016-11-21 21:13:23 -08:00 |
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1577deb324
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travis: delete oldest caches; not newest
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2016-11-21 21:10:29 -08:00 |
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94cc1efadc
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Merge pull request #440 from ucb-bar/tl2-tile
TL2 take-over of the L1
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2016-11-20 20:44:59 -08:00 |
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28c6be90ab
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[rocket] require refillcycesperbeat == 1 and remove flowthroughserializer
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2016-11-20 19:36:51 -08:00 |
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ff9b5bf8fc
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[rocket] nbdcache release bugfix
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2016-11-20 19:07:06 -08:00 |
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e68795421a
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remove L2 regressions for now
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2016-11-19 20:11:20 -08:00 |
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3f47d5b5eb
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[rocket] re-enable working NBDcache (passes Tracegen)
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2016-11-19 19:19:16 -08:00 |
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c31b41a7ac
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[tl2] add grant finisher comment
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2016-11-19 19:16:43 -08:00 |
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9dd12545d0
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[Rocket] Send correct type for iomshr reqs
Also contain grow param bugfix
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2016-11-19 19:04:06 -08:00 |
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32a1c27441
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rocket: disable nbdcache until it's fully ported
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2016-11-18 19:55:24 -08:00 |
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452bb2fc80
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dcache fix TinyConfig
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2016-11-18 19:50:34 -08:00 |
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d1328a6b6f
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rocketchip: remove most uses of GlobalAddrMap
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2016-11-18 19:38:02 -08:00 |
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2976fd84e4
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[rocket] resolve cde/config conflicts
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2016-11-18 19:11:34 -08:00 |
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8b908465e0
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[tl2] convert NBDcache to TL2 (WIP; compiles but untested)
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2016-11-18 19:04:06 -08:00 |
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5f1cc19d71
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[tl2] fix comment explaining permissions
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2016-11-18 19:02:17 -08:00 |
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10112da4e7
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[tl2] won't need putthrough opcode
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2016-11-18 19:02:17 -08:00 |
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001d9821bd
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Merge remote-tracking branch 'origin/master' into tl2-tile
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2016-11-18 18:19:41 -08:00 |
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5b594ced29
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Plic: support 0 interrupts gracefully
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2016-11-18 18:07:44 -08:00 |
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13ec3853ed
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junctions: get unit tests running again
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2016-11-18 17:38:46 -08:00 |
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10dd6070ad
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groundtest: gracefully handle zero uncached ports
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2016-11-18 17:26:28 -08:00 |
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03bca77b33
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tilelink2 Metadata: cannot assert data good when !valid
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2016-11-18 17:16:12 -08:00 |
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be8121eeaf
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coreplex: fix clock crossing
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2016-11-18 17:15:57 -08:00 |
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0082d713af
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coreplex: disable Stateless config until we implement adapter
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2016-11-18 16:23:16 -08:00 |
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8059d33217
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groundtest: simplify FancyMemtestConfig for now
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2016-11-18 16:18:33 -08:00 |
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04b9a68ea6
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MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3
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2016-11-18 16:18:33 -08:00 |
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cd19bf65b8
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regression: fix bad regression that deadlocks SoC with illegal D stall
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2016-11-18 16:18:33 -08:00 |
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5f7fa3dae5
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regression: remove illegal test which reuses the same ID
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2016-11-18 16:18:33 -08:00 |
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a6188efc41
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rocketchip: break infinite Config loops
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2016-11-18 16:18:33 -08:00 |
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37a3c22639
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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40daea2e15
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util: Config scheme supporting up with ++
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2016-11-18 16:18:30 -08:00 |
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e5febcfa33
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rocketchip: there are no more useful parameters to dump
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2016-11-18 14:31:42 -08:00 |
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30425d1665
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rocketchip: eliminate all Knobs
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2016-11-18 14:31:42 -08:00 |
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119ccae9af
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rocketchip: don't use explicit cde namespace
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2016-11-18 14:31:42 -08:00 |
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87cbd5c893
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Merge pull request #439 from ucb-bar/add-chip-configs
Add various granular configs.
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2016-11-18 12:12:50 -08:00 |
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bab504cc3f
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Add various granular and composable configs.
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2016-11-18 11:30:07 -08:00 |
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5bd343bac8
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[rocket] d_last && d.fire() => d_done
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2016-11-17 18:42:59 -08:00 |
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1ddccb1b33
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[rocket] add TODO for single cycle ack
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2016-11-17 18:42:59 -08:00 |
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94086f2270
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[tl2] broadcast hub probe port width bugfix
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2016-11-17 18:42:59 -08:00 |
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960c2723ab
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[tl2] MemoryOpCategories: use def to supply Cat'd consts
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2016-11-17 18:42:59 -08:00 |
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179c93db42
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tilelink2 broadcast: make it controlled via Config
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2016-11-17 17:26:49 -08:00 |
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f4ca5ea1f3
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rocketchip: match simulated memory width to ExtMem.beatBytes
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2016-11-17 15:40:47 -08:00 |
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12d0d8bea2
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rocketchip: remove obsolete bus configuration
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2016-11-17 14:30:15 -08:00 |
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