1
0
Commit Graph

65 Commits

Author SHA1 Message Date
Wesley W. Terpstra
c85486e67c travis: don't give up if gcc is slow to build riscv-tools 2017-06-13 16:59:31 -07:00
Henry Cook
80a3278139 travis: travis_wait to 80 2017-06-13 14:24:40 -07:00
Wesley W. Terpstra
4679545b60 travis: front-load the longer running tests and tolerate no output (#779) 2017-06-02 20:41:26 -07:00
Colin Schmidt
ada5439c3e dont use env to force caches to be the same (#754) 2017-05-18 18:46:29 -07:00
Colin Schmidt
d0c00eccb9 caches don't transfer across sudo flag changes 2017-05-18 11:33:23 -07:00
Colin Schmidt
617dd6fe1e try travis suggestion on the jvm stages 2017-05-18 11:06:43 -07:00
Colin Schmidt
66d660ff60 use YAML to condense script replication 2017-05-17 14:41:04 -07:00
Colin Schmidt
0c382204d4 give them all stages 2017-05-17 12:38:52 -07:00
Colin Schmidt
62a54e6bdb inline the env matrix 2017-05-17 12:36:49 -07:00
Colin Schmidt
2f3e22aff6 matrix outside after jobs 2017-05-17 12:34:11 -07:00
Colin Schmidt
f3775cbbbf try moving matrix into jobs 2017-05-17 12:31:13 -07:00
Colin Schmidt
b7dc415522 maybe this will order them with deploy last 2017-05-17 12:28:01 -07:00
Colin Schmidt
b9fc169367 try another stages organization 2017-05-17 12:24:41 -07:00
Colin Schmidt
83a5230e91 change install to script? 2017-05-17 12:13:31 -07:00
Colin Schmidt
bce613ce38 try using a new travis staging feature
The idea is to let us avoid building the tools
for each SUITE
2017-05-17 11:58:09 -07:00
Palmer Dabbelt
23706113c2 Bump riscv-tools, to get some -mcmodel=medany fixes (#739) 2017-05-11 21:04:32 -07:00
Henry Cook
bcaee9834c travis_wait 30 2017-03-30 13:22:33 -07:00
Wesley W. Terpstra
e74226564c travis: add dependency on device-tree-compiler 2017-03-24 20:59:33 -07:00
Wesley W. Terpstra
d4272db067 travis: only run 4 jobs at once (#593)
We can only run 4 at a time; 5 causes the test time to double.
In the past we had a 50minute build deadline, but that's fixed.
2017-03-18 04:14:50 -07:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550)
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
Henry Cook
c981f8b4f3 More travis job re-balancing (#481)
* [travis] Depend on pre-built docker images rather than travis cache
2016-12-11 22:02:46 -08:00
Henry Cook
9fb7934a37 WIP PR to figure out why travis is failing (#471)
Make travis use a docker image with pre-built toolchain and verilator
2016-12-04 13:10:13 -08:00
Henry Cook
837d207064 [travis] split up groundtest into two suites 2016-11-23 12:27:40 -08:00
Wesley W. Terpstra
3d1a7bd6d3 travis: build verilator and toolchain as part of install 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra
ea3ec89676 travis: split RocketSuite into three smaller tests suites 2016-11-21 21:13:23 -08:00
Wesley W. Terpstra
1577deb324 travis: delete oldest caches; not newest 2016-11-21 21:10:29 -08:00
Colin Schmidt
cb8878c931 Don't build any hurricane branches
Don't mean to eat up travis bandwidth but shared branches sometimes get made.
2016-10-21 16:26:41 -07:00
Yunsup Lee
97809b183f refactor unittest framework
as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
Howard Mao
8906097250 have Travis cache the entire verilator directory 2016-09-04 15:05:30 -07:00
Howard Mao
40bd87bce4 cache the verilator install in travis 2016-08-19 13:45:23 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
33d5905c50 don't synthesize vsim verilog in Travis 2016-08-09 18:24:59 -07:00
Andrew Waterman
2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Howard Mao
63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao
d6ba0437ff merge different configs into regression suites to reduce travis build times 2016-06-24 13:02:29 -07:00
Howard Mao
5edb448a1f get rid of slow DualCoreConfig in Travis for now 2016-06-22 16:09:14 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Palmer Dabbelt
e617bb8aa8 Start testing Chisel 3 in Travis
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis.  This disables Chisel 2 Travis tests because they're
too slow.
2016-06-15 14:01:22 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Howard Mao
5337c7d22d add more complicated memtests to travis 2016-03-31 18:42:14 -07:00
Howard Mao
e77900f540 Revert "switch back to Chisel2 for verilog build for now"
This reverts commit 3673365b08.
2016-03-30 19:00:38 -07:00
Howard Mao
3673365b08 switch back to Chisel2 for verilog build for now 2016-03-29 20:16:07 -07:00
Howard Mao
265a82427e add DefaultL2Config and DualCoreConfig to travis 2016-03-29 20:16:07 -07:00
Howard Mao
2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Palmer Dabbelt
39cf945efb Use Chisel 3 to build verilog on Travis
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip.  We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
2016-03-01 13:03:24 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00