Andrew Waterman
c84848afa6
Report ITIM uncorrectable errors over D-channel
2017-11-06 12:32:45 -08:00
Andrew Waterman
3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM ( #1079 )
...
Workaround: disable interrupts and then do:
.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
2017-10-31 00:49:56 -07:00
Henry Cook
66e4bfc2d9
rocket: TIMs should never be cached
2017-10-11 18:22:52 -07:00
Andrew Waterman
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
Wesley W. Terpstra
0a287df0f7
Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles
2017-09-27 16:28:10 -07:00
Henry Cook
05112b49a3
Merge branch 'master' into tl-error
2017-09-27 14:50:17 -07:00
Wesley W. Terpstra
5323cf88dd
util: add Option.unzip
2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3
diplomacy: eliminate some wasted IdentityNodes using cross-module refs
2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
b9a2e4c243
diplomacy: API beautification
2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4
diplomacy: change API to auto-create node bundles => cross-module refs
2017-09-22 15:01:39 -07:00
Henry Cook
30c8c8c517
Revert "try to give seqmems clearer names"
...
This reverts commit 8db5bbbae0
.
This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
2017-09-21 18:02:32 -07:00
Henry Cook
a887baa615
rocket: base trait for reporting ecc errors
2017-09-21 14:58:47 -07:00
Andrew Waterman
9b828a2640
Only look at error signal on last beat
2017-09-20 15:15:21 -07:00
Andrew Waterman
034ea722f4
Report I$ errors
2017-09-20 00:05:07 -07:00
Henry Cook
8db5bbbae0
try to give seqmems clearer names
2017-09-19 13:41:11 -07:00
Andrew Waterman
a45997d03f
Separate I$ parity error from miss signal
...
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
2017-08-04 16:59:21 -07:00
Andrew Waterman
f483bab4aa
Fix I$ miss perfctr
...
The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
Andrew Waterman
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
Wesley W. Terpstra
9804bdc34e
tilelink: remove obsolete addr_lo signal ( #895 )
...
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Andrew Waterman
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
Andrew Waterman
438abc76d2
Handle TL errors in L1 I$
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Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
Wesley W. Terpstra
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
...
This reverts commit 48390ed604
.
2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
Henry Cook
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
Colin Schmidt
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
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* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
Andrew Waterman
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
Wesley W. Terpstra
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
Andrew Waterman
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
Scott Johnson
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
Andrew Waterman
398600d4da
Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready
2017-05-04 00:57:29 -07:00
Andrew Waterman
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
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@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
Henry Cook
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
Andrew Waterman
d24d8ff84b
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb
Fetch smaller parcels from the I$
2017-04-24 02:01:15 -07:00
Andrew Waterman
2e09253d26
Revive I$ parity option
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Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
Andrew Waterman
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
Andrew Waterman
70e7e90c02
Remove splitMetadata option from L1 caches
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This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
Andrew Waterman
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
Wesley W. Terpstra
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
Andrew Waterman
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
Henry Cook
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00