304 lines
12 KiB
Scala
304 lines
12 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import config._
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import diplomacy._
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import tile._
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import uncore.tilelink2._
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import uncore.util.Code
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import util._
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import Chisel.ImplicitConversions._
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case class ICacheParams(
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nSets: Int = 64,
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nWays: Int = 4,
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rowBits: Int = 128,
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nTLBEntries: Int = 32,
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cacheIdBits: Int = 0,
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ecc: Option[Code] = None,
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itimAddr: Option[BigInt] = None,
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blockBytes: Int = 64) extends L1CacheParams {
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def replacement = new RandomReplacement(nWays)
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}
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trait HasL1ICacheParameters extends HasL1CacheParameters with HasCoreParameters {
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val cacheParams = tileParams.icache.get
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}
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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val addr = UInt(width = vaddrBits)
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}
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class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
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with HasRocketCoreParameters {
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lazy val module = new ICacheModule(this)
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val masterNode = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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val icacheParams = tileParams.icache.get
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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val slaveNode = icacheParams.itimAddr.map { itimAddr =>
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val wordBytes = coreInstBytes * fetchWidth
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TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(AddressSet(itimAddr, size-1)),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsPutFull = TransferSizes(1, wordBytes),
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supportsPutPartial = TransferSizes(1, wordBytes),
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supportsGet = TransferSizes(1, wordBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = wordBytes,
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minLatency = 1)))
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}
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}
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val hartid = UInt(INPUT, hartIdLen)
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val req = Decoupled(new ICacheReq).flip
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val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
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val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val resp = Valid(UInt(width = coreInstBits * fetchWidth))
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val invalidate = Bool(INPUT)
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val tl_out = outer.masterNode.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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}
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// get a tile-specific property without breaking deduplication
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object GetPropertyByHartId {
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def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {
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PriorityMux(tiles.zipWithIndex.collect { case (t, i) if f(t).nonEmpty => (hartId === i) -> f(t).get })
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}
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}
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class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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with HasL1ICacheParameters {
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val io = new ICacheBundle(outer)
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val edge_out = outer.masterNode.edgesOut.head
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val tl_out = io.tl_out.head
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val edge_in = outer.slaveNode.map(_.edgesIn.head)
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val tl_in = io.tl_in.map(_.head)
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(!usingVM || pgIdxBits >= untagBits)
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val scratchpadOn = RegInit(false.B)
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val scratchpadMax = tl_in.map(tl => Reg(UInt(width = log2Ceil(nSets * (nWays - 1)))))
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def lineInScratchpad(line: UInt) = scratchpadMax.map(scratchpadOn && line <= _).getOrElse(false.B)
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def addrMaybeInScratchpad(addr: UInt) = if (outer.icacheParams.itimAddr.isEmpty) false.B else {
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val base = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.icache.flatMap(_.itimAddr.map(_.U)), io.hartid)
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addr >= base && addr < base + outer.size
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}
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def addrInScratchpad(addr: UInt) = addrMaybeInScratchpad(addr) && lineInScratchpad(addr(untagBits+log2Ceil(nWays)-1, blockOffBits))
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def scratchpadWay(addr: UInt) = addr.extract(untagBits+log2Ceil(nWays)-1, untagBits)
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def scratchpadWayValid(way: UInt) = way < nWays - 1
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def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits)
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val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B)
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val s1_slaveValid = RegNext(s0_slaveValid, false.B)
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val s2_slaveValid = RegNext(s1_slaveValid, false.B)
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val s3_slaveValid = RegNext(false.B)
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val s_ready :: s_request :: s_refill :: Nil = Enum(UInt(), 3)
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val refill_addr = Reg(UInt(width = paddrBits))
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val s1_tag_hit = Wire(Vec(nWays, Bool()))
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val s1_any_tag_hit = s1_tag_hit.reduce(_||_) || Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr))
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val s1_valid = Reg(init=Bool(false))
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val s1_hit = s1_valid && s1_any_tag_hit
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val s1_miss = s1_valid && state === s_ready && !s1_any_tag_hit
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io.req.ready := !(tl_out.d.fire() || s0_slaveValid || s3_slaveValid)
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val s0_valid = io.req.fire()
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val s0_vaddr = io.req.bits.addr
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s1_valid := s0_valid
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when (s1_miss) { refill_addr := io.s1_paddr }
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val (_, _, refill_done, refill_cnt) = edge_out.count(tl_out.d)
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tl_out.d.ready := !s3_slaveValid
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require (edge_out.manager.minLatency > 0)
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val repl_way = if (isDM) UInt(0) else {
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// pick a way that is not used by the scratchpad
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val v0 = LFSR16(tl_out.a.fire())(log2Up(nWays)-1,0)
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var v = v0
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for (i <- log2Ceil(nWays) - 1 to 0 by -1) {
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val mask = nWays - (BigInt(1) << (i + 1))
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v = v | (lineInScratchpad(Cat(v0 | mask.U, refill_idx)) << i)
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}
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assert(!lineInScratchpad(Cat(v, refill_idx)))
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v
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}
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val entagbits = code.width(tagBits)
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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when (refill_done) {
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val tag = code.encode(refill_tag)
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tag_array.write(refill_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (tl_out.d.fire()) {
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// clear bit when refill starts so hit-under-miss doesn't fetch bad data
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
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}
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val invalidate = Wire(init = io.invalidate)
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when (invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s1_tag_disparity = Wire(Vec(nWays, Bool()))
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val wordBits = coreInstBits * fetchWidth
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val s1_dout = Wire(Vec(nWays, UInt(width = code.width(wordBits))))
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val s0_slaveAddr = tl_in.map(_.a.bits.address).getOrElse(0.U)
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val s1s3_slaveAddr = Reg(UInt(width = log2Ceil(outer.size)))
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val s1s3_slaveData = Reg(UInt(width = wordBits))
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for (i <- 0 until nWays) {
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val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
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val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
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val scratchpadHit = scratchpadWayValid(i) &&
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Mux(s1_slaveValid,
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lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i,
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addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i)
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val s1_vb = vb_array(Cat(UInt(i), s1_idx)) && !s1_slaveValid
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s1_tag_disparity(i) := s1_vb && code.decode(tag_rdata(i)).error
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s1_tag_hit(i) := scratchpadHit || (s1_vb && code.decode(tag_rdata(i)).uncorrected === s1_tag)
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}
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assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
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require(tl_out.d.bits.data.getWidth % wordBits == 0)
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val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = code.width(wordBits)))) }
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for ((data_array, i) <- data_arrays zipWithIndex) {
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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val wen = (tl_out.d.fire() && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(tl_out.d.fire(), (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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Mux(s3_slaveValid, row(s1s3_slaveAddr),
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Mux(s0_slaveValid, row(s0_slaveAddr),
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row(s0_vaddr))))
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when (wen) {
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val data = Mux(s3_slaveValid, s1s3_slaveData, tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i))
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val way = Mux(s3_slaveValid, scratchpadWay(s1s3_slaveAddr), repl_way)
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data_array.write(mem_idx, Vec.fill(nWays)(code.encode(data)), (0 until nWays).map(way === _))
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}
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val dout = data_array.read(mem_idx, !wen && s0_ren)
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when (wordMatch(Mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr))) {
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s1_dout := dout
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}
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}
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// output signals
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outer.latency match {
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case 1 =>
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require(code.isInstanceOf[uncore.util.IdentityCode])
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require(outer.icacheParams.itimAddr.isEmpty)
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io.resp.bits := Mux1H(s1_tag_hit, s1_dout)
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io.resp.valid := s1_hit
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case 2 =>
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val s2_valid = RegNext(s1_valid && !io.s1_kill, Bool(false))
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val s2_hit = RegNext(s1_hit)
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val s2_tag_hit = RegEnable(s1_tag_hit, s1_valid || s1_slaveValid)
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val s2_dout = RegEnable(s1_dout, s1_valid || s1_slaveValid)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid || s1_slaveValid).asUInt.orR
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val s2_data_decoded = code.decode(s2_way_mux)
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val s2_disparity = s2_tag_disparity || s2_data_decoded.error
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when (s2_valid && s2_disparity) { invalidate := true }
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io.resp.bits := s2_data_decoded.uncorrected
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io.resp.valid := s2_valid && s2_hit && !s2_disparity
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tl_in.map { tl =>
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val respValid = RegInit(false.B)
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tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid)
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val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
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when (s0_slaveValid) {
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val a = tl.a.bits
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s1s3_slaveAddr := tl.a.bits.address
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s1s3_slaveData := tl.a.bits.data
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when (edge_in.get.hasData(a)) {
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val enable = scratchpadWayValid(scratchpadWay(a.address))
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when (!lineInScratchpad(scratchpadLine(a.address))) {
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scratchpadMax.get := scratchpadLine(a.address)
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when (enable) { invalidate := true }
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}
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scratchpadOn := enable
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}
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}
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assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
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when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
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&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) {
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// handle correctable errors on CPU accesses to the scratchpad.
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// if there is an in-flight slave-port access to the scratchpad,
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// report the a miss but don't correct the error (as there is
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// a structural hazard on s1s3_slaveData/s1s3_slaveAddress).
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s3_slaveValid := true
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s1s3_slaveData := s2_data_decoded.corrected
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s1s3_slaveAddr := Cat(OHToUInt(s2_tag_hit), io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0))
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}
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respValid := s2_slaveValid || (respValid && !tl.d.ready)
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when (s2_slaveValid) {
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when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }
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def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
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s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt
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}
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tl.d.valid := respValid
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tl.d.bits := Mux(edge_in.get.hasData(s1_a),
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edge_in.get.AccessAck(s1_a, UInt(0)),
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edge_in.get.AccessAck(s1_a, UInt(0), UInt(0)))
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tl.d.bits.data := s1s3_slaveData
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// Tie off unused channels
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tl.b.valid := false
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tl.c.ready := true
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tl.e.ready := true
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}
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}
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tl_out.a.valid := state === s_request && !io.s2_kill
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tl_out.a.bits := edge_out.Get(
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fromSource = UInt(0),
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toAddress = (refill_addr >> blockOffBits) << blockOffBits,
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lgSize = lgCacheBlockBytes)._2
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tl_out.b.ready := Bool(true)
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tl_out.c.valid := Bool(false)
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tl_out.e.valid := Bool(false)
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assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))
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// control state machine
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switch (state) {
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is (s_ready) {
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when (s1_miss && !io.s1_kill) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request) {
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when (tl_out.a.ready) { state := s_refill }
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when (io.s2_kill) { state := s_ready }
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}
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}
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when (refill_done) {
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assert(state === s_refill)
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state := s_ready
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}
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}
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