riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,731 Commits 1 Branch 0 Tags 13 MiB
c28c23150d
Commit Graph

34 Commits

Author SHA1 Message Date
Andrew Waterman
b2351c5fbf Use consistent casing 2017-07-06 11:16:56 -07:00
Andrew Waterman
438abc76d2 Handle TL errors in L1 I$ 
Cache the error bit in the tag array; report precisely on access.
 2017-07-06 01:02:11 -07:00
Wesley W. Terpstra
fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Henry Cook
5552f23294 tims: explictly name them for generated address map 2017-06-20 17:18:29 -07:00
Colin Schmidt
675f183dd2 refactor ICache to be reusable by other frontends (#808) 
* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction
 2017-06-20 08:21:01 -07:00
Andrew Waterman
16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Wesley W. Terpstra
d25ad10592 diplomacy: require masters to have a name 2017-06-02 15:52:20 -07:00
Andrew Waterman
b2b4c1abcd Separate tag ECC and data ECC options (#761) 2017-05-23 12:51:48 -07:00
Scott Johnson
1b3b228790 ITIM supports PutPartial 2017-05-04 00:57:52 -07:00
Andrew Waterman
398600d4da Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready 2017-05-04 00:57:29 -07:00
Andrew Waterman
d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Henry Cook
e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Andrew Waterman
d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew Waterman
061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Andrew Waterman
a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Wesley W. Terpstra
0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Andrew Waterman
11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Henry Cook
d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Wesley W. Terpstra
fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Henry Cook
e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Henry Cook
74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Henry Cook
540502f96d Convert frontend and icache to diplomacy/tl2 (#486) 
* [rocket] file capitalization

* [rocket] cacheDataBits &etc in HasCoreParameters

* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters

* [rocket] frontend and icache now diplomatic
 2016-12-12 17:38:55 -08:00