riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra
feae216f05 clint: output interrupts in the correct direction 2017-09-27 15:18:42 -07:00
Henry Cook
05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry Cook
652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Henry Cook
5d08b37dab Merge pull request #1019 from freechipsproject/move-rocket-int-sync 
Move rocket output interrupt syncronizers
 2017-09-27 14:46:02 -07:00
Wesley W. Terpstra
9307092d14 coreplex: draw the FrontBus at the bottom and SystemBus at the top 2017-09-27 14:20:39 -07:00
Henry Cook
f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Andrew Waterman
78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Wesley W. Terpstra
e07d86aecd rocket: flip interrupt rendering so cores are on top 2017-09-27 12:46:29 -07:00
Andrew Waterman
583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra
1fda05970a rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:33:08 -07:00
Wesley W. Terpstra
ce01ab2700 RegisterRouter: correctly create interrupts vector 2017-09-27 12:27:16 -07:00
Wesley W. Terpstra
0268959c24 rocket: move interrupt synchronizers to correct side of crossing 2017-09-27 12:02:04 -07:00
Wesley W. Terpstra
e35d3df6ea diplomacy: detect and report cycles in the diplomatic graph 2017-09-27 11:46:06 -07:00
Wesley W. Terpstra
5af08966d8 coreplex: fix WithoutTLMonitors 
closes #1017
 2017-09-27 00:57:18 -07:00
Wesley W. Terpstra
d87536ff8b diplomacy: make NodeHandle recursively composable 2017-09-26 18:47:16 -07:00
Wesley W. Terpstra
31a934bec0 coreplex: buses are now LazyModules with LazyScope 2017-09-26 14:58:56 -07:00
Wesley W. Terpstra
da40573a64 diplomacy: replace LazyModule.stack with an optional scope 2017-09-26 14:56:50 -07:00
Wesley W. Terpstra
a2b423d647 diplomacy: add LazyScope to post-hoc add children to a LazyModule 2017-09-26 14:40:45 -07:00
Wesley W. Terpstra
a27e853101 diplomacy: move rendering properties to edges 
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
 2017-09-26 13:24:36 -07:00
Wesley W. Terpstra
76c2aa1661 diplomacy: introduce the typing-saving SimpleNodeImp 2017-09-26 12:28:59 -07:00
Wesley W. Terpstra
870ed3d219 diplomacy: fix the order of auto signals 2017-09-26 11:56:55 -07:00
Wesley W. Terpstra
d22ec1eddf diplomacy: beautify node signal prefixes 2017-09-26 11:56:53 -07:00
Henry Cook
45d26ea130 Merge pull request #1015 from freechipsproject/coherence-manager 
coreplex: clean up coherence manager attachment point
 2017-09-26 11:09:48 -07:00
Henry Cook
9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
Wesley W. Terpstra
0111213bea ValName: trim whitespace from symbol names 2017-09-25 17:47:40 -07:00
Wesley W. Terpstra
fef5054cec diplomacy: disambiguate names only when necessary 
If two (or more) 'auto_' things have the same name, append _0 and _1 to them.

The order of definitions is unaffected; ie:
  a => a_0
  b => b_0
  b => b_1
  c => c
  a => a_1
 2017-09-25 16:12:34 -07:00
pbing
a86a9c5564 Fix omitted parameter (#1014) 2017-09-25 14:11:28 -07:00
Wesley W. Terpstra
5323cf88dd util: add Option.unzip 2017-09-25 12:06:31 -07:00
Wesley W. Terpstra
60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
bc225a4e82 diplomacy: place Monitors inside LazyModules sinks 
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.

Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
 2017-09-22 23:36:17 -07:00
Wesley W. Terpstra
cfb7f13408 diplomacy: capture SourceInfo at point of := in Edge parameters 2017-09-22 22:25:56 -07:00
Wesley W. Terpstra
16969eb1f6 diplomacy: spelling fix 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra
9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra
53f6999ea8 Splitter: reuse TLCustom node instead of special diplomacy case 2017-09-22 14:58:39 -07:00
Wesley W. Terpstra
6fa5250e1f config: fix warning 2017-09-22 14:58:36 -07:00
Wesley W. Terpstra
17ba209ed0 coreplex: name LazyModules 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
1fedabcb55 tilelink: invoke LazyModule() at point of monitor binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
dfc815f4d3 rocket: invoke LazyModule at point of use/binding 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
87d597c70d ahb apb: remove unintentional var 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
d89ee9d9d4 nodes: grab a name on construction 2017-09-22 14:38:47 -07:00
Wesley W. Terpstra
3656e975a1 diplomacy: ValName captures val bindings for Nodes 2017-09-22 14:38:47 -07:00
Henry Cook
5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire 
Halt and Catch Fire
 2017-09-22 09:30:30 -07:00
Henry Cook
81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook
30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook
e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook
28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook
a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Megan Wachs
ffa3ab29ac Merge pull request #1006 from freechipsproject/async_reset_reg 
async_reset_reg: Don't randomize the register if rst is asserted anyway
 2017-09-21 11:48:04 -07:00
Jim Lawson
4f58aab26f Bumpplugins - add sbt-coverage (#1004) 
Don't advance to plugin versions that are incompatible with current chisel3 code.
 2017-09-20 17:17:55 -07:00