17 Commits

Author	SHA1	Message	Date
Yunsup Lee	c03c09ec31	update for rocket-chip release	2014-08-31 20:26:55 -07:00
Yunsup Lee	e4b56b5d0e	generate verilog for rekall	2014-03-15 15:31:04 -07:00
Yunsup Lee	5128298e8a	allow chisel to elaborate Modules outside of the ReferenceChip package	2014-02-05 03:29:23 -08:00
Stephen Twigg	e50c5180cd	Merge branch 'master' into hwacha	2013-11-14 16:03:55 -08:00
Ben Keller	c137cf1a46	Added line to fix race condition in sbt compile; fixed .gitignores	2013-11-08 15:30:08 -08:00
Stephen Twigg	7da65434ee	Initial commit for the hwacha reference-chip/rocket re-integration.	2013-10-30 20:44:02 -07:00
Andrew Waterman	3c1d1f7981	Fix(?) SBT race by defining subproject build order	2013-10-29 13:27:36 -07:00
Henry Cook	fc9c676fc1	add chisel and hardfloat back as sub-projects, bump other sub-projects	2013-09-26 12:01:46 -07:00
Stephen Twigg	69daae0dae	Add dependency resolvers to build.scala to fix build script	2013-09-05 14:56:41 -07:00
Henry Cook	b06d33da2f	Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes	2013-08-19 19:54:41 -07:00
Henry Cook	4d916b56e3	Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.	2013-07-24 23:28:43 -07:00
Andrew Waterman	7330deb13a	print stack trace if elaboration fails	2012-11-20 05:39:48 -08:00
Andrew Waterman	7bcf59a18f	support continous compilation via "make test" ... for c++ emulator only, for now	2012-11-17 19:58:18 -08:00
Henry Cook	538b23c223	Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles	2012-10-23 12:52:59 -07:00
Henry Cook	17d2bd8926	Initial version of sbt tasks (elaborate task with no parameters)	2012-10-23 12:52:00 -07:00
Huy Vo	24a49350cc	reference chip design	2012-10-09 13:05:56 -07:00
Huy Vo	93a0182b96	everything to get emulator working	2012-10-01 19:30:11 -07:00