Rimas Avizienis
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c42d8149b7
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
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2011-11-17 23:50:45 -08:00 |
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Rimas Avizienis
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db87924fbf
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made eret instruction take an illegal inst exception when ET is set
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2011-11-14 14:35:10 -08:00 |
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Rimas Avizienis
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cd6e463320
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added ei and di instructions
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2011-11-14 13:48:49 -08:00 |
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Rimas Avizienis
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b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
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2011-11-14 04:13:13 -08:00 |
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Rimas Avizienis
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890bfa7c48
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added IPIs and timer interrupts
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2011-11-14 03:24:02 -08:00 |
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Rimas Avizienis
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5b29765917
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synced up with supervisor mode state in latest ISA simulator
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2011-11-14 01:37:20 -08:00 |
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Rimas Avizienis
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345f950eff
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added timer interrupt support
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2011-11-13 00:27:57 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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603ede8bfe
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access faults now write badvaddr PCR register with faulting address
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2011-11-10 02:46:09 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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