riscv/rocket-chip
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55 Commits

Author SHA1 Message Date
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee
1cb2d1d7b7 initialize all SRAMs to avoid X propagation problem 2014-09-04 11:06:01 -07:00
Yunsup Lee
763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer
6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00